Verilog

Question

使用 ModelSim PE 学生版 10.4a。为 1-4 demux 编写了一个模块。为该模块编写了一个测试平台。编译正常。尝试模拟时，出现以下错误：

# ** Warning: (vsim-3015) D:/ModelSim/examples/Lab3_3.v(42): [PCDPC] - Port size (1) does not match connection size (4) for port 'in'. The port definition is at: D:/ModelSim/examples/Lab3_3.v(1).
# Time: 0 ns Iteration: 0 Instance: /tb_demux/DA0 File: D:/ModelSim/examples/Lab3_3.v
# ** Error (suppressible): (vsim-3053) D:/ModelSim/examples/Lab3_3.v(42): Illegal output or inout port connection for port 'out'. # Time: 0 ns Iteration: 0 Instance: /tb_demux/DA0 File: D:/ModelSim/examples/Lab3_3.v
# ** Warning: (vsim-3015) D:/ModelSim/examples/Lab3_3.v(42): [PCDPC] - Port size (4) does not match connection size (1) for port 'out'. The port definition is at: D:/ModelSim/examples/Lab3_3.v(1).
# Time: 0 ns Iteration: 0 Instance: /tb_demux/DA0 File: D:/ModelSim/examples/Lab3_3.v

代码是：

module demux(input in, input[1:0] S, output reg[3:0] out);


always @(in or S)
begin
     case(S)
    2'b00: begin
        out[0] = in;
        out[1] = 0;
        out[2] = 0;
        out[3] = 0;
        end
    2'b01: begin
        out[0] = 0;
        out[1] = in;
        out[2] = 0;
        out[3] = 0;
        end
    2'b10: begin
        out[0] = 0;
        out[1] = 0;
        out[2] = in;
        out[3] = 0;
        end
    2'b11: begin
        out[0] = 0;
        out[1] = 0;
        out[2] = 0;
        out[3] = in;
        end
     endcase
end

endmodule   


module tb_demux;
wire[3:0] out;
reg[1:0] S;
reg in;

demux DA0(out, S, in);

initial
begin

    S = 2'b00; in = 0;
    #100 S = 2'b01; in = 1;
    #100 S = 2'b10; in = 0;
    #100 S = 2'b11; in = 1;
end

initial #400 $stop;

initial $monitor("Select = %b, In = %b, Out = %b", S, in, out);
endmodule

似乎无法完成这项工作。谢谢

Answer 1

设计的实例化尚未从测试平台正确完成。设计中的端口被错误地映射到测试台。

将设计的实例化从测试台更改为以下内容：

demux DA0(in,s,out);

最好使用名称实例化设计，而不是在 verilog 中使用顺序，以避免此类端口不匹配。

Answer 2

我明白了。我显然以错误的顺序将变量输入测试台。

正确的行是：

demux DA0(in, S, out);

因此变量的顺序与它们在模块中声明的顺序相同:

module demux(input in, input[1:0] S, output reg[3:0] out);

Verilog - 端口大小与连接大小不匹配

Verilog - Port Size Does Not Match Connection Size

port

modelsim