测试台出错,因为 'DIGITADD' 的 Inout 端口 'A' 必须是网络
Error in testbench as Inout port 'A' of 'DIGITADD' must be a net
module DIGITADD(
input [3:0] A,
input [3:0] B,
input CIN,
output COUT,
output [3:0] SUM
);
reg [4:0] s2;
assign SUM = s2[3:0];
assign COUT = s2[4];
//BCD ADDER PART
always @ ( * )
begin
s2 = A + B + CIN;
if (s2 > 9)
begin
s2 = s2 + 6;
end
end
endmodule
测试台
module DIGITADD_tb(
reg [3:0] A,
reg [3:0] B,
reg CIN,
wire COUT,
wire [3:0] SUM);
DIGITADD uut(
.A(A),
.B(B),
.CIN(CIN),
.COUT(COUT),
.SUM(SUM));
initial begin
$dumpfile("dump.vcd");
$dumpvars(1,DIGITADD_tb);
#10;
#10 A=4'b0000;B=4'b0011;CIN=1'b0;
#10 A=4'b0111;B=4'b1000;CIN=1'b1;
$finish;
end
endmodule
您已经以端口列表的形式在您的测试台中添加了局部变量:
module DIGITADD_tb(
reg [3:0] A,
reg [3:0] B,
reg CIN,
wire COUT,
wire [3:0] SUM);
应该是:
module DIGITADD_tb(); //<-- no ports
reg [3:0] A; //<-- semicolon
reg [3:0] B;
reg CIN;
wire COUT;
wire [3:0] SUM;
module DIGITADD(
input [3:0] A,
input [3:0] B,
input CIN,
output COUT,
output [3:0] SUM
);
reg [4:0] s2;
assign SUM = s2[3:0];
assign COUT = s2[4];
//BCD ADDER PART
always @ ( * )
begin
s2 = A + B + CIN;
if (s2 > 9)
begin
s2 = s2 + 6;
end
end
endmodule
测试台
module DIGITADD_tb(
reg [3:0] A,
reg [3:0] B,
reg CIN,
wire COUT,
wire [3:0] SUM);
DIGITADD uut(
.A(A),
.B(B),
.CIN(CIN),
.COUT(COUT),
.SUM(SUM));
initial begin
$dumpfile("dump.vcd");
$dumpvars(1,DIGITADD_tb);
#10;
#10 A=4'b0000;B=4'b0011;CIN=1'b0;
#10 A=4'b0111;B=4'b1000;CIN=1'b1;
$finish;
end
endmodule
您已经以端口列表的形式在您的测试台中添加了局部变量:
module DIGITADD_tb(
reg [3:0] A,
reg [3:0] B,
reg CIN,
wire COUT,
wire [3:0] SUM);
应该是:
module DIGITADD_tb(); //<-- no ports
reg [3:0] A; //<-- semicolon
reg [3:0] B;
reg CIN;
wire COUT;
wire [3:0] SUM;