错误 - 靠近“：”：语法错误，意外的“：”，需要 IDENTIFIER 或时钟

Question

我创建了自己的 my_macros 文件：

`ifndef MY_MACROS_SV
`define MY_MACROS_SV

// MACRO: 'my_fatal_err
// calls uvm_fatal in case the assertion is not correct
`define my_fatal(condition, msg )\
   assert (condition) else\
`uvm_fatal("FATAL ERROR", msg)\
\
`define add_rand(mem_type, mem)\
   case (mem_type)\
     "int": add_rand_int(mem);\
     "bit": add_rand_bit(mem);\    
     default: `uvm_fatal("FATAL ERROR", "type is not supported")\ 
     endcase  



`endif  //MY_MACROS_SV

mem_type 需要一个字符串，mem 是 class.

的成员

我遇到以下编译错误：

at ..\sv\my_macros.sv(19): near ":": syntax error, unexpected ':', expecting IDENTIFIER or clock.

第 19 行是 default:

Answer 1

分开你的 2 个宏：

`ifndef MY_MACROS_SV
`define MY_MACROS_SV

// MACRO: 'my_fatal_err
// calls uvm_fatal in case the assertion is not correct
`define my_fatal(condition, msg )\
   assert (condition) else\
`uvm_fatal("FATAL ERROR", msg)

`define add_rand(mem_type, mem)\
   case (mem_type)\
     "int": add_rand_int(mem);\
     "bit": add_rand_bit(mem);\    
     default: `uvm_fatal("FATAL ERROR", "type is not supported")\ 
     endcase  



`endif  //MY_MACROS_SV

错误 - 靠近“：”：语法错误，意外的“：”，需要 IDENTIFIER 或时钟

Error - near ":": syntax error, unexpected ':', expecting IDENTIFIER or clock

macros

system-verilog

uvm