内存控制器如何将数据分配给 DIMM？
How does Memory Controller distributes the data to DIMMs?
一个假设的场景是当一台计算机有 2 个 dimm 时，内存控制器如何在两者之间分配数据？
它必须使用地址中的一些位，但是哪些位以及为什么使用这些位。
我会说每个 dimm bank/row 大小是有道理的，因为我们会有大量同时有效的行缓冲区，并且可能会增加带宽。
实际是怎么做到的？ （假设 x86 上的通用 CPU 架构）
Here 他根据他对 Intel Sandy Bridge CPU 的实验展示了一些结果：
Bits 0-5: These are the lower 6 bits of the byte index within a row (i.e. the 6-bit index into a 64-byte cache line).
Bit 6: This is a 1-bit channel number, which selects between the 2 DIMMs.
Bits 7-13: These are the upper 7 bits of the index within a row (i.e. the upper bits of the column number).
Bits 14-16: These are XOR'd with the bottom 3 bits of the row number to give the 3-bit bank number.
Bit 17: This is a 1-bit rank number, which selects between the 2 ranks of a DIMM (which are typically the two sides of the DIMM's circuit board).
Bits 18-32: These are the 15-bit row number.
Bits 33+: These may be set because physical memory starts at physical addresses greater than 0.
一个假设的场景是当一台计算机有 2 个 dimm 时，内存控制器如何在两者之间分配数据？
它必须使用地址中的一些位，但是哪些位以及为什么使用这些位。
我会说每个 dimm bank/row 大小是有道理的，因为我们会有大量同时有效的行缓冲区，并且可能会增加带宽。
实际是怎么做到的？ （假设 x86 上的通用 CPU 架构）
Here 他根据他对 Intel Sandy Bridge CPU 的实验展示了一些结果：
Bits 0-5: These are the lower 6 bits of the byte index within a row (i.e. the 6-bit index into a 64-byte cache line).
Bit 6: This is a 1-bit channel number, which selects between the 2 DIMMs.
Bits 7-13: These are the upper 7 bits of the index within a row (i.e. the upper bits of the column number). Bits 14-16: These are XOR'd with the bottom 3 bits of the row number to give the 3-bit bank number.
Bit 17: This is a 1-bit rank number, which selects between the 2 ranks of a DIMM (which are typically the two sides of the DIMM's circuit board).
Bits 18-32: These are the 15-bit row number.
Bits 33+: These may be set because physical memory starts at physical addresses greater than 0.