JAL："alternate link register" x5 有什么用？
JAL: what is the "alternate link register" x5 for?
RISC-V 规范 v2.2（JAL 指令，第 15 页）说 "standard calling convention"：
The standard software calling convention uses x1 as the return address register and x5 as an alternate link register.
具有以下设计注释：
The alternate link register supports calling millicode routines (e.g., those to save and restore
registers in compressed code) while preserving the regular return address register.
link 注册的备选方案是什么？
我了解到"link register"是存放return上要跳转到的pc的寄存器，millicode/microcode是ISA层以下的低层指令格式。对于围绕 "normal calls" 的某些 (microcode/millicode) 指令，使用 x5 而不是 而不是 x1 的想法是为了避免寄存器改组或泄漏？你有一个典型的用法示例吗？
在 link registers 上的维基百科文章中添加备用 link 寄存器的解释可能会有所帮助，这是我寻找额外信息的地方。
一般来说，毫码指令不应与普通指令相交，需要另一种调用约定来调用毫码过程(from Waterman's PhD Thesis, page 66):
... routines must
have an alternate calling convention since the link register must be preserved during their
execution. Fortunately, unlike ARM and MIPS, RISC-V’s jump-and-link instruction can
write the return address to any integer register, rather than clobbering the ABI-designated
link register. Other than that distinction, these millicode routines behave like ordinary
procedures
一个更具体的原因，为什么要保留 link 寄存器，是因为 millicode 用于实现序言和结尾，因此使用常规调用约定会破坏 link 寄存器和将打败对 prologues/epilogues 使用毫码的整个想法。
Is the idea that x5 is used instead of x1 for certain (microcode/millicode) instructions that surround "normal calls" to avoid register shuffling or a spill?
是的...在某种程度上 "surround"。
Would you have a typical usage example?
请参阅 prologue_2、epilogue_2 来自 Waterman's PhD, page 67
的毫码例程
00: c919 c.beqz a0, 16
02: 016002ef jal t0, prologue_2
06: 842a c.mv s0, a0
08: 157d c.addi a0, -1
0a: ff7ff0ef jal ra, factorial
0e: 02850533 mul a0, a0, s0
12: 0100006f jal x0, epilogue_2
16: 4505 c.li a0, 1
18: 8082 c.jr ra
其中 prologue_2:
00: 1141 c.addi sp, -16
02: e406 c.sdsp ra, 8(sp)
04: e022 c.sdsp s0, 0(sp)
06: 8282 c.jr t0
和epilogue_2：
00: 60a2 c.ldsp ra, 8(sp)
02: 6402 c.ldsp s0, 0(sp)
04: 0141 c.addi sp, 16
06: 8082 c.jr ra
RISC-V 规范 v2.2（JAL 指令，第 15 页）说 "standard calling convention"：
The standard software calling convention uses x1 as the return address register and x5 as an alternate link register.
具有以下设计注释：
The alternate link register supports calling millicode routines (e.g., those to save and restore registers in compressed code) while preserving the regular return address register.
link 注册的备选方案是什么？
我了解到"link register"是存放return上要跳转到的pc的寄存器，millicode/microcode是ISA层以下的低层指令格式。对于围绕 "normal calls" 的某些 (microcode/millicode) 指令，使用 x5 而不是 而不是 x1 的想法是为了避免寄存器改组或泄漏？你有一个典型的用法示例吗？
在 link registers 上的维基百科文章中添加备用 link 寄存器的解释可能会有所帮助，这是我寻找额外信息的地方。
一般来说，毫码指令不应与普通指令相交，需要另一种调用约定来调用毫码过程(from Waterman's PhD Thesis, page 66):
... routines must have an alternate calling convention since the link register must be preserved during their execution. Fortunately, unlike ARM and MIPS, RISC-V’s jump-and-link instruction can write the return address to any integer register, rather than clobbering the ABI-designated link register. Other than that distinction, these millicode routines behave like ordinary procedures
一个更具体的原因，为什么要保留 link 寄存器，是因为 millicode 用于实现序言和结尾，因此使用常规调用约定会破坏 link 寄存器和将打败对 prologues/epilogues 使用毫码的整个想法。
Is the idea that x5 is used instead of x1 for certain (microcode/millicode) instructions that surround "normal calls" to avoid register shuffling or a spill?
是的...在某种程度上 "surround"。
Would you have a typical usage example?
请参阅 prologue_2、epilogue_2 来自 Waterman's PhD, page 67
00: c919 c.beqz a0, 16
02: 016002ef jal t0, prologue_2
06: 842a c.mv s0, a0
08: 157d c.addi a0, -1
0a: ff7ff0ef jal ra, factorial
0e: 02850533 mul a0, a0, s0
12: 0100006f jal x0, epilogue_2
16: 4505 c.li a0, 1
18: 8082 c.jr ra
其中 prologue_2:
00: 1141 c.addi sp, -16
02: e406 c.sdsp ra, 8(sp)
04: e022 c.sdsp s0, 0(sp)
06: 8282 c.jr t0
和epilogue_2：
00: 60a2 c.ldsp ra, 8(sp)
02: 6402 c.ldsp s0, 0(sp)
04: 0141 c.addi sp, 16
06: 8082 c.jr ra