"after" 无法在 Modelsim 中工作

Question

我正在尝试在 Modelsim 中制作串行加法器的行为模型。

因此，在设计中我试图在一个时钟周期后将 Carry_out 传递给 Carry_in。

设计是：

一位，每一个来自两个n位的数，随进位一起进入加法器。

最初进位为 0，但在下一个时钟周期中，前一位加法的 carry_out 再次作为 carry_in 传递，加法是用接下来的两位完成的，一个来自每个数字。

代码如下：

library ieee;

use ieee.std_logic_1164.all;

entity serial_adder is

    port (a,b: in std_logic;
        s: out std_logic;
        cin,cout: inout std_logic);
end serial_adder;

architecture serial_adder_arch of serial_adder is
begin
    process(a,b,cin,cout)
    begin
    if (a='0' and b ='0' and cin ='0')
    then s <='0';
         cout <='0';
    elsif (a='0' and b ='0' and cin ='1')
    then s <='1';
         cout <='0';
    elsif (a='0' and b ='1' and cin ='0')
    then s <='1';
         cout <='0';
    elsif (a='0' and b ='1' and cin ='1')
    then s <='0';
         cout <='1';
    elsif (a='1' and b ='0' and cin ='0')
    then s <='1';
         cout <='0';
    elsif (a='1' and b ='0' and cin ='1')
    then s <='0';
         cout <='1';
    elsif (a='1' and b ='1' and cin ='0')
    then s <='0';
         cout <='1';
    elsif (a='1' and b ='1' and cin ='1')
    then s <='1';
         cout <='1';
    end if;
    cin <= cout after 50 ps;
    end process;

end serial_adder_arch;

模拟后，我发现我使用 'after' 提供的延迟不起作用。我没有延迟，cout 没有分配给 cin

Answer 1

你的模拟器时间分辨率是多少？默认为1ns，延时会四舍五入到分辨率。

尝试vsim -t 50ps将分辨率更改为 50ps。

Answer 2

即使你让这段代码在模拟中工作，它也不会综合，因为等待语句。

参见下面的串行加法器代码。

library ieee;
use ieee.std_logic_1164.all;

--serial adder for N bits. Note that we dont have to mention N here. 
entity serial_adder is
    port(Clk,reset : in std_logic; --clock and reset signal
            a,b,cin : in std_logic;  --note that cin is used for only first iteration.
            s,cout : out std_logic  --note that s comes out at every clock cycle and cout is valid only for last clock cycle.
            );
end serial_adder;

architecture behav of serial_adder is

--intermediate signals.
signal c,flag : std_logic := '0';

begin

process(clk,reset)
--we use variable, so that we need the carry value to be updated immediately.
variable c : std_logic := '0'; 
begin
if(reset = '1') then --active high reset
    s <= '0';
    cout <= c;
    flag <= '0';
elsif(rising_edge(clk)) then
    if(flag = '0') then
        c := cin;  --on first iteration after reset, assign cin to c.
        flag <= '1';  --then make flag 1, so that this if statement isnt executed any more.
    end if; 
    s <= a xor b xor c;  --SUM
    c := (a and b) or (c and b) or (a and c);  --CARRY
end if;
end process;

end behav;

如果你喜欢，那么这里有testbench代码和解释link。

"after" 无法在 Modelsim 中工作

"after" not working in Modelsim

vhdl

modelsim