算术右移在 Verilog HDL 中不起作用

Question

我正在构建一个移位单元，它能够根据提供给它的控制信号进行算术和逻辑右移以及逻辑左移。但是，算术右移运算符输出生成类似于逻辑右移运算符的输出，即不会发生符号扩展。

主要代码

`timescale 1ns / 1ps

module shift_unit(
    input [15:0] a,
    input [3:0] b,
     input clk,
    input isLSL,
    input isLSR,
    input isASR,
    output reg [15:0] result
    );
wire [15:0] LSL_result, LSR_result, ASR_result;

LSL lsl(a, b, clk, isLSL, LSL_result);
LSR lsr(a, b, clk, isLSR, LSR_result);
ASR asr(a, b, clk, isASR, ASR_result);

always@(posedge clk) begin
case({isLSL, isLSR, isASR})
    3'b001: result <= ASR_result;
    3'b010: result <= LSR_result;
    3'b100: result <= LSL_result;
endcase
end

endmodule

LSL代码：

`timescale 1ns / 1ps
module LSL(
    input [15:0] a,
    input [3:0] b,
     input clk,
     input isLSL,
    output [15:0] out
    );

reg [15:0] result;
always@(posedge clk) begin
    if(isLSL)   result = a << b;
end
assign out = result;

endmodule

LSR代码：

`timescale 1ns / 1ps
module LSR(
    input [15:0] a,
    input [3:0] b,
    input clk,
    input isLSR,
    output [15:0] out
    );

reg [15:0] result;
always@(posedge clk) begin
    if(isLSR)   result = a >> b;
end
assign out = result;

endmodule

ASR 代码：

`timescale 1ns / 1ps
module ASR(
    input [15:0] a,
    input [3:0] b,
    input clk,
    input isASR,
    output [15:0] out
    );

reg [15:0] result;
always@(posedge clk) begin
    if(isASR)   result = a >>> b;
end
assign out = result;

endmodule

最后，测试平台：

`timescale 1ns / 1ps

module shift_unit_test;
    reg [15:0] a;
    reg [3:0] b;
    reg clk;
    reg isLSL;
    reg isLSR;
    reg isASR;

    wire [15:0] result;

    shift_unit uut (
        .a(a), 
        .b(b), 
        .clk(clk), 
        .isLSL(isLSL), 
        .isLSR(isLSR), 
        .isASR(isASR), 
        .result(result)
    );

    always #5 clk = ~clk;

    initial begin
        clk = 1'b0;
        a = 16'b1100101011001010;
        b = 4;
        {isLSL, isLSR, isASR} = 3'b100; #100;
        {isLSL, isLSR, isASR} = 3'b010; #100;
        {isLSL, isLSR, isASR} = 3'b001; #100;
    end

endmodule

以上代码已使用 Xilinx ISE 14.7 建模。任何帮助将不胜感激。

Answer 1

您需要使用 signed 信号才能获得符号扩展。

module ASR(
    input wire signed [15:0] a,
    input [3:0] b,
    input clk,
    input isASR,
    output reg signed [15:0] out
    );


always@(posedge clk) begin
    if(isASR)   out = a >>> b;
end

endmodule

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