Verilog error :Assignment under multiple single edges is not supported for synthesis

Question

当我想做一个类似电梯的程序项目时，无论我做什么来编辑我的模块，它总是说：

Assignment under multiple single edges is not supported for synthesis

一些变量：

tar_floor : user input, target floor;
cur_floor : current floor located;
clk_cnt : variable added 1 each time to count.

always @(posedge clk or posedge clr) begin

if(clr)
begin
    cur_floor = 0; //if clear button pressed,clear all statement
    tar_floor=0;
    upordown=0; 
    clk_cnt=0;
    ryg=3'b001; //green
    rgb=3'b111;
end

if(tar_floor==cur_floor) //nothing to do
begin
    clk_cnt=0;
    upordown=0; 
    clk_cnt=0;
    ryg=3'b001; //green
    rgb=3'b111;
end
else 
begin//when up or down  
    clk_cnt = clk_cnt +1;
    if (tar_floor>cur_floor)
    begin
        ryg=3'b100;//red
        if (clk_cnt[27])
            rgb=rgb+1;
        if(clk_cnt[28])
        begin
            if (cur_floor<=6)
                cur_floor=cur_floor+1;
        end
    end

    if (tar_floor<cur_floor)
    begin
        ryg=3'b010;//yello
        if (clk_cnt[27])
            rgb=rgb+1;
        if(clk_cnt[28])
        begin
            if (cur_floor>=1)
                cur_floor=cur_floor-1;
        end
    end
end
end

wire tmp=cur_floor;
mytask_sub A1(.a_to_g(a_to_g),.cur_floor(tmp));//call show sub modudle

endmodule

在 clk_cnt = clk_cnt +1;，它说：

Assignment under multiple single edges is not supported for synthesis

请帮我解决这个错误。

Answer 1

Synthesis 要求您按如下方式构建代码：

always @(posedge clk or posedge clr)
    if(clr)
       // asynchronous statement when clr rises 
       // and any clk rising edge while clr is true
    else
       // synchronous statement when clk rises and clr is false

您缺少 else 子句

Verilog error :Assignment under multiple single edges is not supported for synthesis

Verilog error :Assignment under multiple single edges is not supported for synthesis

verilog