是否可以在结构 verilog 中重复一个门？

Question

我将在 Verilog 中级联多个缓冲器。我的示例如下，我定义了 16 个在结构定义中级联的缓冲区：

BUFX12 BUF01(dummy_wire[1],N62878);
BUFX12 BUF02(dummy_wire[2],dummy_wire[1]);
BUFX12 BUF03(dummy_wire[3],dummy_wire[2]);
BUFX12 BUF04(dummy_wire[4],dummy_wire[3]);
BUFX12 BUF05(dummy_wire[5],dummy_wire[4]);
BUFX12 BUF06(dummy_wire[6],dummy_wire[5]);
BUFX12 BUF07(dummy_wire[7],dummy_wire[6]);
BUFX12 BUF08(dummy_wire[8],dummy_wire[7]);
BUFX12 BUF09(dummy_wire[9],dummy_wire[8]);
BUFX12 BUF10(dummy_wire[10],dummy_wire[9]);
BUFX12 BUF11(dummy_wire[11],dummy_wire[10]);
BUFX12 BUF12(dummy_wire[12],dummy_wire[11]);
BUFX12 BUF13(dummy_wire[13],dummy_wire[12]);
BUFX12 BUF14(dummy_wire[14],dummy_wire[13]);
BUFX12 BUF15(dummy_wire[15],dummy_wire[14]);

由于我要更改测试设计中的缓冲区数量，我正在寻找诸如 for-loop 之类的语法来以自动格式实现以下结构，但我不知道正确的结构. 我想知道是否可能以及正确的语法是什么。此外如果实现有实例名称会更好。

Answer 1

使用实例数组：

wire [15:1] other = {dummy_wire[14:1], N62878};
BUFX12 BUF [15:1] (dummy_wire, other);

Answer 2

您可以根据需要使用生成循环，但@toolic 提供的实例数组解决方案更紧凑：

  assign dummy_wire[0] = N62878;

  generate
    genvar g;
    for (g=1; g<16; g=g+1)
      begin : in_Verilog_2001_you_need_this_and_it_needs_a_name
        BUFX12 BUF(dummy_wire[g],dummy_wire[g-1]);
      end
  endgenerate

Verilog-2005 放宽了有关 generate 的规则。这在 Verilog-2005 中是合法的：

  assign dummy_wire[0] = N62878;

  genvar g;
  for (g=1; g<16; g=g+1)
    BUFX12 BUF(dummy_wire[g],dummy_wire[g-1]);

在 SystemVerilog 中，您可以稍微整理一下：

  assign dummy_wire[0] = N62878;

  for (genvar g=1; g<16; g++)
    BUFX12 BUF(dummy_wire[g],dummy_wire[g-1]);

但就个人而言，我喜欢 Verilog-2001 版本：它更明确。

MCVE:

module M;

  wire [15:0] dummy_wire;
  wire N62878;

  assign dummy_wire[0] = N62878;

  generate
    genvar g;
    for (g=1; g<16; g=g+1)
      begin : in_Verilog_2001_you_need_this_and_it_needs_a_name
        BUFX12 BUF(dummy_wire[g],dummy_wire[g-1]);
      end
  endgenerate

endmodule

https://www.edaplayground.com/x/YWw

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