5 或门行为模型的区别
The differences between 5 behavioral model for OR gate
我想为OR门设计5个行为模型。这些模型有什么区别？每个模型都实现了哪些延迟（惯性延迟和传输延迟），原因是什么？
模型 1：LHS 阻塞
#4 O = (A | B);
模型 2：LHS 非阻塞
#4 O <= (A | B);
模型 3：RHS 阻塞
O = #4 (A | B);
模型 4：RHS 非阻塞
O <= #4 (A | B);
模型 5：连续赋值
assign #4 O = (A | B);
Clifford E. Cummings 有一篇非常好的论文“Correct Methods For Adding Delays To Verilog Behavioral Models”，您可以在其中找到有关在 Verilog 中使用不同延迟模型的一些提示：
阻塞分配延迟模型：
Modeling Guideline: do not place delays on the LHS of
blocking assignments to model combinational logic. This
is a bad coding style.
Testbench Guideline: placing delays on the LHS of
blocking assignments in a testbench is reasonable since
the delay is just being used to time-space sequential input
stimulus events.
RHS 阻塞延迟：
Modeling Guideline: do not place delays on the RHS of
blocking assignments to model combinational logic. This
is a bad coding style.
Testbench Guideline: do not place delays on the RHS of
blocking assignments in a testbench.
General Guideline: placing a delay on the RHS of any
blocking assignment is both confusing and a poor coding
style. This Verilog coding practice should be avoided.
非阻塞分配延迟模型：
Modeling Guideline: do not place delays on the LHS of
nonblocking assignments to model combinational logic.
This is a bad coding style.
Testbench Guideline: nonblocking assignments are less
efficient to simulate than blocking assignments; therefore,
in general, placing delays on the LHS of nonblocking
assignments for either modeling or testbench generation is
discouraged.
RHS 非阻塞延迟：
Recommended Application: Use this coding style to
model behavioral delay-line logic.
Modeling Guideline: place delays on the RHS of
nonblocking assignments only when trying to model
transport output-propagation behavior. This coding style
will accurately model delay lines and combinational logic
with pure transport delays; however, this coding style
generally causes slower simulations.
Testbench Guideline: This coding style is often used in
testbenches when stimulus must be scheduled on future
clock edges or after a set delay, while not blocking the
assignment of subsequent stimulus events in the same
procedural block.
连续分配延迟模型：
RHS delay model is illegal with continuous assignment
前面提到的型号延迟以下型号：
- 为连续赋值添加延迟可以准确地模拟具有惯性延迟的组合逻辑。
- 向非阻塞分配的右侧 (RHS) 添加延迟将使用 transport 准确地建模组合逻辑
延误。
我想为OR门设计5个行为模型。这些模型有什么区别？每个模型都实现了哪些延迟（惯性延迟和传输延迟），原因是什么？
模型 1：LHS 阻塞
#4 O = (A | B);
模型 2：LHS 非阻塞
#4 O <= (A | B);
模型 3：RHS 阻塞
O = #4 (A | B);
模型 4：RHS 非阻塞
O <= #4 (A | B);
模型 5：连续赋值
assign #4 O = (A | B);
Clifford E. Cummings 有一篇非常好的论文“Correct Methods For Adding Delays To Verilog Behavioral Models”，您可以在其中找到有关在 Verilog 中使用不同延迟模型的一些提示：
阻塞分配延迟模型：
Modeling Guideline: do not place delays on the LHS of blocking assignments to model combinational logic. This is a bad coding style.
Testbench Guideline: placing delays on the LHS of blocking assignments in a testbench is reasonable since the delay is just being used to time-space sequential input stimulus events.RHS 阻塞延迟：
Modeling Guideline: do not place delays on the RHS of blocking assignments to model combinational logic. This is a bad coding style.
Testbench Guideline: do not place delays on the RHS of blocking assignments in a testbench.
General Guideline: placing a delay on the RHS of any blocking assignment is both confusing and a poor coding style. This Verilog coding practice should be avoided.非阻塞分配延迟模型：
Modeling Guideline: do not place delays on the LHS of nonblocking assignments to model combinational logic. This is a bad coding style.
Testbench Guideline: nonblocking assignments are less efficient to simulate than blocking assignments; therefore, in general, placing delays on the LHS of nonblocking assignments for either modeling or testbench generation is discouraged.RHS 非阻塞延迟：
Recommended Application: Use this coding style to model behavioral delay-line logic.
Modeling Guideline: place delays on the RHS of nonblocking assignments only when trying to model transport output-propagation behavior. This coding style will accurately model delay lines and combinational logic with pure transport delays; however, this coding style generally causes slower simulations.
Testbench Guideline: This coding style is often used in testbenches when stimulus must be scheduled on future clock edges or after a set delay, while not blocking the assignment of subsequent stimulus events in the same procedural block.连续分配延迟模型：
RHS delay model is illegal with continuous assignment
前面提到的型号延迟以下型号：
- 为连续赋值添加延迟可以准确地模拟具有惯性延迟的组合逻辑。
- 向非阻塞分配的右侧 (RHS) 添加延迟将使用 transport 准确地建模组合逻辑 延误。