"Readline called past the end of file" 错误 VHDL

"Readline called past the end of file" error VHDL

我需要读取 VHDL 文件,但出现错误: "Line 57: Readline called past the end of file mif_file"

impure function init_mem(mif_file_name : in string) return mem_type is
    file mif_file : text open read_mode is mif_file_name;
    variable mif_line : line;
    variable temp_bv : bit_vector(DATA_WIDTH-1 downto 0);
    variable temp_mem : mem_type;
begin
    for i in mem_type'range loop
        readline(mif_file, mif_line);
        read(mif_line, temp_bv);
        temp_mem(i) := to_stdlogicvector(temp_bv);
    end loop;       
return temp_mem;
end function;

如评论部分所述,您尝试阅读的内容超出了文件中的内容,您可以通过检查 for loop 中是否到达文件末尾来避免错误case 改为分配默认值。

impure function init_mem(mif_file_name : in string) return mem_type is
    file mif_file : text open read_mode is mif_file_name;
    variable mif_line : line;
    variable temp_bv : bit_vector(DATA_WIDTH-1 downto 0);
    variable temp_mem : mem_type;
begin
    for i in mem_type'range loop
        if(not endfile(mif_file)) then
            readline(mif_file, mif_line);
            read(mif_line, temp_bv);
            temp_mem(i) := to_stdlogicvector(temp_bv);
        else
            temp_mem(i) := default_value_to_be_defined;
        end if;
    end loop;       
return temp_mem;
end function;

或者如果不想设置默认值可以退出for loop

impure function init_mem(mif_file_name : in string) return mem_type is
    file mif_file : text open read_mode is mif_file_name;
    variable mif_line : line;
    variable temp_bv : bit_vector(DATA_WIDTH-1 downto 0);
    variable temp_mem : mem_type;
begin
    for i in mem_type'range loop
        if(not endfile(mif_file)) then
            readline(mif_file, mif_line);
            read(mif_line, temp_bv);
            temp_mem(i) := to_stdlogicvector(temp_bv);
        else
            exit;
        end if;
    end loop;       
return temp_mem;
end function;