带有宏的难以理解的 case 表达式

Question

为了准备考试，我想复习一些 Verilog 代码，我使用 https://www.jdoodle.com/ 作为编译器。但出于某种原因，这些案例会引发错误。

jdoodle.v:20: syntax error
jdoodle.v:20: error: Incomprehensible case expression.
jdoodle.v:21: syntax error
jdoodle.v:21: error: Incomprehensible case expression.
jdoodle.v:22: syntax error
jdoodle.v:22: error: Incomprehensible case expression.
jdoodle.v:23: syntax error
jdoodle.v:23: error: Incomprehensible case expression.
jdoodle.v:24: syntax error
jdoodle.v:24: error: Incomprehensible case expression.

module ALU (
    input wire [2:0]OPCODE,
    input wire [31:0]A,
                     B,
    output reg [31:0]RESULT
);

`define ADD 0;
`define SUB 1;
`define MULT 2;
`define DIV 3;
`define MOD 4;

function [31:0] calculate (
    input [31:0] A,
    input [31:0] B,
    input [2:0] OPCODE
); 
    case (OPCODE)
        `ADD: calculate = A + B;
        `SUB: calculate = A - B;
        `MULT: calculate = A * B;
        `DIV: calculate = A / B;
        `MOD: calculate = A % B;
    endcase
endfunction

always @(A or B or OPCODE)
    RESULT = calculate(A, B, OPCODE);

endmodule

非常感谢任何帮助。

Answer 1

删除定义末尾的分号。

您将 ADD 定义为 0;
因此您的代码变为：

case (OPCODE)
    0; : calculate = A + B;
    1; : calculate = A - B;
    2; : calculate = A * B;
    3; : calculate = A / B;
    4; : calculate = A % B;
endcase

带有宏的难以理解的 case 表达式

Incomprehensible case expression with macros

verilog