为什么我的输出没有被赋值？

Question

我正在为一个较大项目的一部分开发解码器。我有两个计数器作为该模块的输入。其中一个计数 0 - 15，另一个在第一个计数器达到 15 时递增一次。根据计数器的值，解码器输出不同的值。通常为 0、1 或 -1，但有时必须为 0.707 或 -0.707，我们暂时使用定点数来处理。

我遇到的问题是，使用我的测试代码，我无法在计数器启动后立即分配我的输出运行。我已将我的模拟代码简化为一个非常简单的测试，我在其中非常快速地触发复位开关，然后将第一个计数器分配为 1，然后将第二个计数器分配为 1，这应该使解码器将 1 分配给输出。它一直在输出 'XXXXXX'。

在此之前，我有一长串 'else if' 语句执行赋值，但我遇到了同样的错误。

我敢肯定这个错误真的很简单，但我还没有看到它。

Verilog 代码：

`timescale 1ns / 1ps

module Decoder_W
(
    input clk,
    input rst,
    input [31:0] counter,
    input [31:0] stage_counter,
    output reg [31:0] out_W
);

always @ (posedge(clk)) 
begin

if (rst == 1)
    out_W <= 0;

else if (stage_counter == 32'd1)
    begin 
        case (counter)
            32'd0: out_W <= 1;
            32'd1: out_W <= -1;
            32'd2: out_W <= 1;
            32'd3: out_W <= -1;
            32'd4: out_W <= 1;
            32'd5: out_W <= -1;
            32'd6: out_W <= 1;
            32'd7: out_W <= -1;
            32'd8: out_W <= 0;
            32'd9: out_W <= 0;
            32'd10: out_W <= 0;
            32'd11: out_W <= 0;
            32'd12: out_W <= 0;
            32'd13: out_W <= 0;
            32'd14: out_W <= 0;
            32'd15: out_W <= 0; 
            default out_W <= 0;
        endcase
     end

else if (stage_counter == 32'd2)
    begin
        case (counter)
            32'd0: out_W <= 1;
            32'd1: out_W <= 0;
            32'd2: out_W <= -1;
            32'd3: out_W <= 0;
            32'd4: out_W <= 1;
            32'd5: out_W <= 0;
            32'd6: out_W <= -1;
            32'd7: out_W <= 0;
            32'd8: out_W <= 0;
            32'd9: out_W <= -1;
            32'd10: out_W <= 0;
            32'd11: out_W <= 1;
            32'd12: out_W <= 0;
            32'd13: out_W <= -1;
            32'd14: out_W <= 0;
            32'd15: out_W <= 1;
            default out_W <= 0;       
         endcase
     end

else if (stage_counter == 32'd3)
    begin
        case (counter)
            32'd0: out_W <= 1;
            32'd1: out_W <= 0;
            32'd2: out_W <= 0;
            32'd3: out_W <= 32'b11111111111111111110100101100000;
            32'd4: out_W <= -1;
            32'd5: out_W <= 32'b11111111111111111110100101100000;
            32'd6: out_W <= 0;
            32'd7: out_W <= 32'b00000000000000000001011010100000;
            32'd8: out_W <= 0;
            32'd9: out_W <= 32'b11111111111111111110100101100000;
            32'd10: out_W <= -1;
            32'd11: out_W <= 32'b11111111111111111110100101100000;
            32'd12: out_W <= 0;
            32'd13: out_W <= 32'b00000000000000000001011010100000;
            32'd14: out_W <= 1;
            32'd15: out_W <= 32'b00000000000000000001011010100000;
            default out_W <= 0;       
         endcase
     end

else
    out_W <= 0;

end
endmodule

测试平台：

`timescale 1ns / 1ps

module testbench;

reg clk = 0;
reg rst = 0;
reg [31:0] counter = 0;
reg [31:0] stage_counter = 0;
wire [31:0] out_W = 0;

Decoder_W test
(
    .clk(clk),
    .rst(rst),
    .counter(counter),
    .stage_counter(stage_counter),
    .out_W(out_W)
);

integer i = 0;

always #5 clk = ~clk;
initial 
begin
#10 rst = 0;
#10 rst = 1;
#10 rst = 0;
#10 stage_counter = 1;
#10 counter = 0;
#10 counter = 1;
#30

$finish;
end
endmodule

模拟输出：

Answer 1

由于争用，您的输出结果为 X。测试台中的 out_W 有 2 个驱动程序：wire，它连续驱动 0，Decoder_W 模块，它驱动 1，然后驱动 'hffff_ffff.

要修复它，请不要为 wire 赋值。变化：

wire [31:0] out_W = 0;

至：

wire [31:0] out_W;

Answer 2

out_W 是输出线，因此您不应该初始化它。试试下面的代码。

`timescale 1ns / 1ps

 module testbench;

  reg clk;
  reg rst;
  reg [31:0] counter;
  reg [31:0] stage_counter;
  wire [31:0] out_W;

  Decoder_W test
  (
    .clk(clk),
    .rst(rst),
    .counter(counter),
    .stage_counter(stage_counter),
    .out_W(out_W)
   );

   integer i = 0;

   always #5 clk = ~clk;
   initial 
   begin
         clk = 0;
         rst = 0;
         counter = 0;
         stage_counter = 0;
     #10 rst = 1;
     #10 rst = 0;
     #10 stage_counter = 1;
     #10 counter = 0;
     #10 counter = 1;
     #30
    $finish;
  end
 endmodule

为什么我的输出没有被赋值？

Why is my output not getting assigned a value?

verilog