Always block with posedge triggering 以某种方式在时间 0 工作

Question

我写了一段基本的 Verilog 代码。

    `timescale 1ns / 1ps
module lab3_2(
            input[3:0] command,
            input CLK,
            input mode,
            output reg [7:0] total_time1,
            output reg [7:0] total_time0
     );
     initial begin
     total_time1 = 8'b00000000;
     total_time0 = 8'b00000000;

     end

     always @(posedge CLK) begin

            if(total_time1 == 8'b00000001 && total_time0 == 8'b00001001)
                begin
                total_time0 <= 8'b00000000;
                total_time1 <= 8'b00000000;
                end
            else if(total_time0 == 8'b00001001)
                begin
                total_time1 <= 8'b00000001;
                total_time0 <= 8'b00000000;
                end
            else
                begin
                total_time0 <= total_time0 + 8'b00000001;
                end
        end

endmodule

计时到20，total_time1显示最左边的数字，total_time0显示最右边的数字。
如果 total_time1 = 1 并且 total_time0 = 5，那么这是 always 块第 15 次起作用。

我的问题是，当我尝试这个测试平台时：

`timescale 1ns /1ps

module lab3_2_testbench;

reg[3:0] command;
reg CLK;
reg mode ;
wire[7:0] total_time1;
wire[7:0] total_time0;


lab3_2 uut(
.command(command),
.CLK(CLK),
.mode(mode),
.total_time1(total_time1),
.total_time0(total_time0)
);


initial CLK = 1;
    always #5 CLK = ~CLK;

initial begin
$monitor("Time=%t | command=%b mode=%b| total_time1=%b total_time0=%b   CLK=%b      ", $time, command, mode,total_time1,total_time0,CLK);
mode = 0 ;


command = 4'b0000;

$display("Current simulation time = %t",$time);
    #10;
    $display("Current simulation time = %t",$time);

    $finish;





end

endmodule

我得到的输出是：

Time=                   0 | command=0000 mode=0| total_time1=00000000 total_time0=00000001   CLK=1      
Time=                5000 | command=0000 mode=0| total_time1=00000000 total_time0=00000001   CLK=0      
Current simulation time =                10000
Stopped at time : 10 ns : File "/home/bs04/e2237006/Desktop/liy/testbench_part2.v" Line 35 **

为什么total_time0在时间0时等于1？不应该是0吗？我认为增加 total_time0 的唯一方法是通过触发 always 块，但我是如何设法在时间 0 触发 always 块的？

根据我的代码，CLK 以 1 开头。

Answer 1

在testbench中，CLK声明为reg，reg的初始值为x。然后将其分配给 1。由于 x 到 1 的转换是一个 posedge，因此会触发 always 块，并执行 else 子句，递增 total_time0.

Always block with posedge triggering 以某种方式在时间 0 工作

Always block with posedge triggering somehow works at time 0

verilog