+1 逻辑的 4 位计数器 D 触发器

Question

我正在尝试通过 Verilog 实现这个带有 +1 逻辑的 D 触发器计数器。但是，我收到了很多关于 net 的多个常量驱动程序的错误代码。谁能帮帮我？这是到目前为止的代码：

module LAB (clk, clear, Enable, Q);

input clk, clear, Enable;   
    
output[3:0] Q; 
                
reg[3:0] Q;

wire D;

    
assign D = Q;
    
always @ (posedge clk)

begin

if (!clear)

Q <= 1'b0;

else

Q <= D;

end
    
always @ (Enable)

begin

if (Enable == 1)

Q <= D + 1;

else
 
Q <= D;

end 
    
endmodule

这是我收到的错误代码：

Error (10028): Can't resolve multiple constant drivers for net "Q[3]" at 


LAB.v(17)
Error (10029): Constant driver at LAB.v(9)


Error (10028): Can't resolve multiple constant drivers for net "Q[2]" at LAB.v(17)


Error (10028): Can't resolve multiple constant drivers for net "Q[1]" at LAB.v(22)


Error (10028): Can't resolve multiple constant drivers for net "Q[0]" at LAB.v(22)


Error (12153): Can't elaborate top-level user hierarchy


Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 6 errors, 4 warnings

Error: Peak virtual memory: 4613 megabytes


Error: Processing ended: Sun Apr 19 18:39:09 2020


Error: Elapsed time: 00:00:01


Error: Total CPU time (on all processors): 00:00:00


Error (293001): Quartus II Full Compilation was unsuccessful. 8 errors, 4 
warnings

Answer 1

您有 2 个不同的 always 块，它们驱动相同的寄存器 Q。您可以将单独的 always 块视为单独的硬件设备。因此，在您的情况下，您有 2 个连接的触发器输出。这违反了硬件和综合规则。它还会在模拟过程中产生问题。

修复它的唯一方法是创建一个单独的 always 块，它定义了驱动翻牌所需的所有逻辑，如下所示：

always @ (posedge clk or negedge clear) begin
    if (!clear)
        Q <= 1'b0;
    else if (enable)
        Q <= D + 1;
    else 
        Q <= D;
end

我不是在这里评论你的逻辑，只是举一个例子，应该消除 Q 的多个驱动程序的所有错误。

+1 逻辑的 4 位计数器 D 触发器

A 4-bit counter D flip flop with + 1 logic

verilog