verilog error:syntax error-Is there a missing '::'?

Question

** Error: line(27): near "=": syntax error, unexpected '='.

** Error: line(27): (vlog-13205) Syntax error found in the scope following 'Q'. Is there a missing '::'?

module LS161a(
    input [3:0] D,        // Parallel Input
    input CLK,            // Clock
    input CLR_n,          // Active Low Asynchronous Reset
    input LOAD_n,         // Enable Parallel Input
    input ENP,            // Count Enable Parallel
    input ENT,            // Count Enable Trickle
    output [3:0]Q,        // Parallel Output    
    output RCO            // Ripple Carry Output (Terminal Count)
); 
wire [3:0]temp;

always @(posedge CLK)
begin
    if (CLR_n==0)
        temp<=0000;
    else if (CLR_n==1)
    begin
        if (LOAD_n == 0)

            temp<=D;
        else if (ENP==1 & ENT==1)
            temp<=temp+1;
    end 
end
Q=temp;                                 //line 27
RCO = temp[3]& temp[2]& temp[1]& temp[0]& ENT;
//end 
endmodule 

Answer 1

错误指向行：

Q=temp;

您需要使用 assign 关键字对 wire 进行连续赋值。对于 RCO，您可能也遇到了类似的错误。我还遇到了 temp 赋值的第三个编译错误。由于它是在 always 块中分配的，因此必须将其声明为 reg 而不是 wire。我更改了您代码中的 3 行以修复所有这些错误（标记为 ////）。

module LS161a(
    input [3:0] D,        // Parallel Input
    input CLK,            // Clock
    input CLR_n,          // Active Low Asynchronous Reset
    input LOAD_n,         // Enable Parallel Input
    input ENP,            // Count Enable Parallel
    input ENT,            // Count Enable Trickle
    output [3:0]Q,        // Parallel Output    
    output RCO            // Ripple Carry Output (Terminal Count)
); 
reg [3:0]temp; ////

always @(posedge CLK)
begin
    if (CLR_n==0)
        temp<=0000;
    else if (CLR_n==1)
    begin
        if (LOAD_n == 0)

            temp<=D;
        else if (ENP==1 & ENT==1)
            temp<=temp+1;
    end 
end

assign Q=temp; ////
assign RCO = temp[3]& temp[2]& temp[1]& temp[0]& ENT; ////
endmodule