如何修复 VHDL 错误 "type of identifier xxx does not agree with its usage as xxx type"？

Question

我是 VHDL 新手。我的代码现在看起来像这样：

...

entity g14_lpm is
port ( i_clk    : in std_logic;
        i_rstb  : in std_logic;
         i_x     : in std_logic_vector(31 downto 0);
         i_y     : in std_logic_vector(31 downto 0);
         o_xx, o_yy : out std_logic_vector(64 downto 0)
);
end g14_lpm;

architecture arc of g14_lpm is
signal r_x : signed(31 downto 0);
signal r_y : signed(31 downto 0);
signal xx  : signed(63 downto 0);
signal yy  : signed(63 downto 0);
signal xy  : signed(53 downto 0);
component LPM_MULT

...

port ( DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
         DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
         ACLR  : in std_logic := '0';
         CLOCK : in std_logic := '0';
         CLKEN : in std_logic := '1';
         RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end component;

begin
------------------------COMPONENT INSTANTIATION---------------------------------
        mult1 : LPM_MULT generic map (
                  LPM_WIDTHA => 32,
                  LPM_WIDTHB => 32,
                  LPM_WIDTHP => 64,
                  LPM_REPRESENTATION => "SIGNED",
                  LPM_PIPELINE => 4
        )

--ERROR IS HERE↓

        port map ( DATAA => i_x, DATAB => i_x, CLOCK => i_clk, RESULT => xx );

--ERROR IS HERE↑

...

        p_mult : process (i_clk, i_rstb)
        begin

...

        elsif (rising_edge(i_clk)) then
            r_x <= signed(i_x);
            r_y <= signed(i_y);

        o_xx <= std_logic_vector ('0' & xx - yy);
        o_yy <= std_logic_vector (r_X*r_y & '0');

        end if;
        end process p_mult;


end arc;

我在第 49 行遇到两个错误，突出显示的是 type of identifier "xx" does not agree with its usage "std_logic_vector" type 和 cannot associate formal port "RESULT" of mode "out" with an expression。

我不确定这部分要更改什么，手册中提供了大部分代码。

我该如何解决这个问题？

Answer 1

要么使用辅助信号

signal result : std_logic_vector(63 downto 0);

port map ( 
    DATAA => i_x, 
    DATAB => i_x, 
    CLOCK => i_clk, 
    RESULT => result
);
xx <= signed(result);

或者也许他们可以直接投射 - 从来没有试图说实话 - 比如

port map ( 
    DATAA => i_x, 
    DATAB => i_x, 
    CLOCK => i_clk, 
    signed(RESULT) => xx 
);

如前所述here

如何修复 VHDL 错误 "type of identifier xxx does not agree with its usage as xxx type"？

How to fix the VHDL error "type of identifier xxx does not agree with its usage as xxx type"?

vhdl