If 语句 Verilog 中的多个条件

Question

我有以下 if/else 声明：

if ((write1 && write 2) && ( read_reg1== read_reg2))
      reg_file[write_reg1] =  write_data1;
    else if((write1 && write 2) && ( read_reg1!=read_reg2)) begin 
      reg_file[write_reg2] =  write_data2;
      reg_file[write_reg1] =  write_data1;
    end
    else if (write1)
      reg_file[write_reg1] =  write_data1;
    else 
      reg_file[write_reg2] =  write_data2;

我收到这些错误：

ERROR VCP2000 "Syntax error. Unexpected token: 2[_UNSIGNED_NUMBER]. Expected tokens: '[' , '(*' , '(' , 'with' , '++' ... ." "design.sv" 23  28
ERROR VCP2000 "Syntax error. Unexpected token: ). Expected tokens: '(*' , '++' , '--'." "design.sv" 23  58
ERROR VCP2000 "Syntax error. Unexpected token: 2[_UNSIGNED_NUMBER]. Expected tokens: '[' , '(*' , '(' , 'with' , '++' ... ." "design.sv" 25  31
ERROR VCP2000 "Syntax error. Unexpected token: ). Expected tokens: '(*' , '++' , '--'." "design.sv" 25  60
ERROR VCP2000 "Syntax error. Unexpected token: else[_ELSE]. Expected tokens: '#' , ''' , '(' , ';' , '@' ... ." "design.sv" 29  9

那么这里的问题是什么？

Answer 1

您的变量名中有一个 space。

write 2

应该是

write2

请注意，这会出现两次 - 在“if”和第一个“else if”中

Answer 2

对于在寻找语法参考时偶然发现此问题的人，以下是“4.1.9 逻辑运算符”和“9.4”部分的摘录one of the revisions of the Verilog standard.

中的条件语句"

这是if语句的语法:

conditional_statement ::= 
    if ( expression )
        statement_or_null [ else statement_or_null ]
    | if_else_if_statement

If the expression evaluates to true (that is, has a nonzero known value), the first statement shall be executed. If it evaluates to false (has a zero value or the value is x or z), the first statement shall not execute. If there is an else statement and expression is false, the else statement shall be executed.

这是关于 逻辑运算符 将多个条件组合在一个表达式中：

The operators logical and (&&) and logical or (||) are logical connectives. The result of the evaluation of a logical comparison shall be 1 (defined as true), 0 (defined as false), or, if the result is ambiguous, the unknown value (x). The precedence of && is greater than that of ||, and both are lower than relational and equality operators.

A third logical operator is the unary logical negation operator (!). The negation operator converts a nonzero or true operand into 0 and a zero or false operand into 1.

If 语句 Verilog 中的多个条件

Multiple conditions in If statement Verilog

verilog