FSM 输出永远不会被设置

Question

我无法使用 gtkwave 在 iverilog 上模拟以下 FSM。在 gtkwave 上查看时，给定测试台的输入正在发生变化。另外，我不认为逻辑是错误的。也没有编译错误，但仍然没有输出。我无法修复错误。

代码 :

module seq_0110(sequence_in,clock,reset,detector_out
    );
input clock; // clock signal
input reset; // reset input
input sequence_in; // binary input
output reg detector_out; // output of the sequence detector
//parameter  Zero=3'b000, // "Zero" State
//  One=3'b001, // "One" State
//  OneZero=3'b011, // "OneZero" State
//  OneZeroOne=3'b010, // "OnceZeroOne" State
//  OneZeroOneOne=3'b110;// "OneZeroOneOne" State
reg [1:0] current_state, next_state; // current state and next state
// sequential memory of the Moore FSM
always @(posedge clock, posedge reset)
begin
 if(reset==1) 
 current_state <=2'b00;// when reset=1, reset the state of the FSM to "Zero" State
 else
 current_state <= next_state; // otherwise, next state
end 
// combinational logic of the Moore FSM
// to determine next state 
always @(current_state,sequence_in)
begin
 case(current_state) 
 2'b00:begin
  if(sequence_in==1)
   next_state <= 2'b00;
  else
   next_state <= 2'b01;
 end
 2'b01:begin
  if(sequence_in==1)
   next_state <= 2'b10;
  else
   next_state <= 2'b01;
 end
 2'b10:begin
  if(sequence_in==1)
   next_state <= 2'b11;
  else
   next_state <= 2'b01;
 end 
 2'b11:begin
  if(sequence_in==1)
   next_state <= 2'b00;
  else
   next_state <= 2'b01;
 end

 default:next_state <= 2'b00;
 endcase
end
// combinational logic to determine the output
// of the Moore FSM, output only depends on current state
always @(current_state)
begin 
 case(current_state) 
 2'b00:   detector_out <= 1'b0;
 2'b01:   detector_out <= 1'b0;
 2'b10:  detector_out <= 1'b0;
 2'b11:  detector_out <=(sequence_in==1)?1'b0:1'b1;

 default:  detector_out <= 1'b0;
 endcase
end 
endmodule

Teshbench

`timescale 1ns / 1ps

module seq_0110_t;

 // Inputs
 reg sequence_in;
 reg clock;
 reg reset;

 // Outputs
 wire detector_out;

 // Instantiate the Sequence Detector using Moore FSM
 seq_0110 uut (
  .sequence_in(sequence_in), 
  .clock(clock), 
  .reset(reset), 
  .detector_out(detector_out)
 );
 initial 
begin
 clock = 0;
 forever #5 clock = ~clock;
 end 

 initial 
begin
  // Initialize Inputs
  $dumpfile("seq_0110.vcd");
  $dumpvars(0,seq_0110_t);
  $monitor($time,"sequence_in=%b detector_out=%b",sequence_in,detector_out);
  sequence_in = 0;
  reset = 1;
  // Wait 100 ns for global reset to finish
  #30;
      reset = 0;
  #40;
  sequence_in = 0;
  #10;
  sequence_in = 0;
  #10;
  sequence_in = 1; 
  #20;
  sequence_in = 1; 
  #20;
  sequence_in = 0; 
  #20;
  sequence_in = 0;  
  #20;
  sequence_in = 1;  
  #20;
  sequence_in = 1;  
  #20;
  sequence_in = 0;  
  #20;
  sequence_in = 0;  

// Add stimulus here
  #10 $finish;

 end

endmodule

Answer 1

使用您的输入刺激，输出 (detector_out) 始终为 0。

将 detector_out 设置为 1 的唯一方法是在以下语句中：

 2'b11:  detector_out <=(sequence_in==1)?1'b0:1'b1;

这意味着 current_state 必须是 3 而 sequence_in=0。但是，在您的输入波中，当 current_state=3.

时 sequence_in 始终为 1

如果您认为逻辑没有错，请调整输入刺激以达到那种情况。这是一种方法（参考我的 <----- 评论）：

 initial 
begin
  // Initialize Inputs
  $dumpfile("seq_0110.vcd");
  $dumpvars(0,seq_0110_t);
  $monitor($time,"sequence_in=%b detector_out=%b",sequence_in,detector_out);
  sequence_in = 0;
  reset = 1;
  // Wait 100 ns for global reset to finish
  #30;
      reset = 0;
  #45;                             // <------ more delay
  sequence_in = 0;
  #10;
  sequence_in = 0;
  #10;
  sequence_in = 1; 
//  #20;                          <------ commented out
//  sequence_in = 1;              <------ commented out
  #20;
  sequence_in = 0; 
  #20;

我减少了时间sequence_in=1。这会在时间 115 设置 detector_out=1:

           0sequence_in=0 detector_out=0
          95sequence_in=1 detector_out=0
         115sequence_in=0 detector_out=1
         125sequence_in=0 detector_out=0
         155sequence_in=1 detector_out=0
         195sequence_in=0 detector_out=0

我还有其他一些建议。对于您的 2 个组合 always 块，您应该考虑使用隐式敏感列表 (always @*) 和块分配 (=)。

FSM 输出永远不会被设置

FSM output never gets set

verilog