在 VHDL 中使用信号作为输入或输出

Question

我写这段代码。我想在 r = '1' 时使用数据作为输出，在 w = '1' 时使用数据作为输入。我尝试了，但没有用。它有一个错误（错误：D:/modelism project/project/memory.vhd(42): Target of signal assignment is not a signal.）。你能帮我修一下吗？

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------------------------------------------
Entity memory is
    Generic (bits: integer := 16;
         words: integer := 16);
    port (  r, w: in std_logic;-------read and write------------
        addr: in std_logic_vector(11 downto 0);
        data: inout std_logic_vector(bits-1 downto 0));

End memory;
----------------------------------------------------------------------
Architecture memory of memory is
    Type vector_array is array (0 to words-1) of std_logic_vector(bits-1 downto 0);
    constant memory: vector_array :=
                    ( "0000000000000000",
                      "0000000000000001",
                      "0000000000000010",
                      "0000000000000011",
                      "0000000000000100",
                      "0000000000000101",
                      "0000000000000110",
                      "0000000000000111",
                      "0000000000000000",
                      "0000000000000001",
                      "0000000000000010",
                      "0000000000000011",
                      "0000000000000100",
                      "0000000000000101",
                      "0000000000000110",
                      "0000000000000111");
    signal loc: integer range 0 to words - 1;
begin
    process(r, w)
    begin
        if(r = '1') then
            loc <= to_integer(signed(addr));
            data <= memory(loc);
        elsif(w = '1') then
            loc <= to_integer(signed(addr));
            memory(loc) <= data;
        end if;
    end process;
End memory;

Answer 1

当你声明常量时，它就是一个固定值。您以后无法更改它。相反，您可以将内存声明为信号并声明一个 init 常量来初始化它，如下所示：

constant init: vector_array :=
                ( "0000000000000000",
                  "0000000000000001",
                  "0000000000000010",
                  "0000000000000011",
                  "0000000000000100",
                  "0000000000000101",
                  "0000000000000110",
                  "0000000000000111",
                  "0000000000000000",
                  "0000000000000001",
                  "0000000000000010",
                  "0000000000000011",
                  "0000000000000100",
                  "0000000000000101",
                  "0000000000000110",
                  "0000000000000111");
signal memory: vector_array := init;

此外，您需要注意来自 inout 类型的端口，它们应该被分配一个值。

想想当r='0'和w='0'时会发生什么？？

Answer 2

可以使用三态缓冲器实现“inout”引脚。为此，您可以在没有过程的情况下描述它，因为它与“时钟”或时间无关，而是取决于另一个信号的固定值。

像这样：

当“pin_we”为“1”时，“pin_Dout”连接到“pin_io”，否则变为高阻抗 'Z'。

当你想读取引脚时使用“pin_io”，当你想要写入时使用“pin_Dout”

Entity Main is
  port (pin_io : inout std_logic);
End Main;

Architecture Behavioral of Main is
        signal  pin_Dout : std_logic;
        signal  pin_we  : std_logic := '0'; 
Begin

    pin_io <= pin_Dout when pin_we='1' else 'Z'; -- when pin_we='0';

End Behavioral;

在 VHDL 中使用信号作为输入或输出

Use a singnal as an input or output in VHDL

vhdl