如何删除以下代码中的错误：

Question

每次我尝试编译时，它都会在我的代码的第 7 行和第 13 行显示以下错误。即在 [2:0] 函数附近和 [31:0] Data_in 附近。编译器给出以下错误：

在“[”附近：语法错误，意外的“[”，需要 IDENTIFIER 或 TYPE_IDENTIFIER 或 NETTYPE_IDENTIFIER。

我该怎么办？

module rv32i(clk, reset);// Input is read from files
input clk, reset;
//Wires are defined to connect to various components

// ALU wires
wire rz;
wire [2:0] funct, [31:0] v1, [31:0] v2, [31:0] result;

// Instruction Memory Wires
wire [31:0] ins;

// Register File Wires
wire [31:0] Data_in, [31:0] Data_Out2, [4:0] Write_Addr;

// Data Memory Wires
wire [31:0] read_data;
wire write_en, read_en;

// Controller Wires
wire reg_dst, jump, branch, mem_read, mem_to_reg,
 alu_op, mem_write, alu_src, reg_write;

// Immediate instruction wires
wire [31:0] imm_ext;

//Connections of the processor
memory m(
    .ins(ins),
    .imm(imm_ext[6:0]),
    .branch(branch),
    .rz(rz),
    .jump(jump),
    .clk(clk)
    );

controller c(
    .clk(clk),
    .reset(reset),
    .opcode(ins[6:0]),
    .reg_dst(reg_dst),
    .jump(jump),
    .branch(branch),
    .mem_read(mem_read),
    .mem_to_reg(mem_to_reg),
    .alu_op(alu_op),
    .mem_write(mem_write),
    .alu_src(alu_src),
    .reg_write(reg_write)
    );

data_mem d(
    .d_addr(result),
    .write_en(write_en),
    .read_en(read_en),
    .write_data(Data_Out2),
    .read_data(read_data),
    .clk(clk)
    );

mux2_1 mem_reg(
    .a(result),
    .b(read_data),
    .s(mem_to_reg),
    .c(Data_in)
    );

mux2_1_5 ins_reg(
    .a(ins[24:20]),
    .b(ins[11:7]),
    .s(reg_dst),
    .c(Write_Addr)
    );

Registers r(
    .Data_in(Data_in),
    .Data_Out1(v1),
    .Data_Out2(Data_Out2),
    .Read_Addr_1(ins[19:15]),
    .Read_Addr_2(ins[24:20]),
    .Write_Addr(Write_Addr),
    .Write_Enable(reg_write),
    .clk(clk)
    );

alu_control ac(
    .ins_func(ins[14:12]),
    .ins_out(funct),
    .alu_op(alu_op)
    );

extend alu_imm(
    .a1(ins[31:20]),
    .a2(imm_ext)
    );

mux2_1 alu_mux(
    .a(Data_Out2), .b(imm_ext), .s(alu_src), .c(v2)
    );

ALU a(
    .clk(clk),
    .reset(reset),
    .funct(funct),
    .v1(v1),
    .v2(v2),
    .rz(rz),
    .result(result)
    );

endmodule

我找不到任何错误，但无法编译。

Answer 1

每个电汇声明只允许使用一组打包维度。你需要把它分开

wire [2:0] funct, [31:0] v1, [31:0] v2, [31:0] result;

应该是

wire [2:0] funct;
wire [31:0] v1, v2, result;

下面的另一行也是如此。

如何删除以下代码中的错误：

How do I remove the errors in the following code:

verilog