Error (10170): Verilog HDL syntax error at CRC_configurable.v(62) near text: "integer"; expecting "end"

Question

我正在使用 Quartus Prime Lite Edition 并有一个 case 声明：

S2: begin
            dat[WID_DAT-1 :1] <= dat[WID_DAT-2 :0];
            dat[0] <= 0;
            crc[0] <= crc_temp[0];
            integer i;
            for (i = 1; i < WID_CRC; i = i+1) begin
                crc[i] <= crc_temp[i] ^ crc[i-1];
            end
            
            if(count != 0) begin
                r_ns <= S2;
                count <= count -1;
            end
            
            else begin
            r_ns <= S_DONE;
            done <= 1;
            end
        end

并在我开始 Anlysis & Elaboration 时收到错误消息：

Error (10170): Verilog HDL syntax error at CRC_configurable.v(62) near text: "integer"; expecting "end".

为什么会这样，我该如何避免？

Answer 1

您不得在 begin/end 块的中间声明 integer。您可以将 integer 声明行移到 always 块之外（在它之前）。

integer i;

always ... 
...
S2: begin
            dat[WID_DAT-1 :1] <= dat[WID_DAT-2 :0];
            dat[0] <= 0;
            crc[0] <= crc_temp[0];
            for (i = 1; i < WID_CRC; i = i+1) begin
                crc[i] <= crc_temp[i] ^ crc[i-1];
            end

或者，如果您为开始块命名，您应该能够在 begin 行之后立即声明 integer。

Error (10170): Verilog HDL syntax error at CRC_configurable.v(62) near text: "integer"; expecting "end"

Error (10170): Verilog HDL syntax error at CRC_configurable.v(62) near text: "integer"; expecting "end"

for-loop

verilog

case