SystemVerilog 名称别名

Question

SystemVerilog 是否为模块实例和枚举启用别名？例如，我该如何编码：

enum logic {foo, bar} myEnum
enum logic {baz, qux} myEnum

即baz和qux分别是foo和bar的别名。

Answer 1

它们不能是别名，但可以是 casted/converted。参考IEEE Std 1800-2012§6.19.4数值表达式中的枚举类型。 LRM 示例：

typedef enum {Red, Green, Blue} Colors;
typedef enum {Mo,Tu,We,Th,Fr,Sa,Su} Week;
Colors C;
Week W;
int I;
C = Colors'(C+1);            // C is converted to an integer, then added to
                             // one, then converted back to a Colors type
C = C + 1; C++; C+=2; C = I; // Illegal because they would all be
                             // assignments of expressions without a cast
C = Colors'(Su);             // Legal; puts an out of range value into C
I = C + W;                   // Legal; C and W are automatically cast to int

Answer 2

let 构造可以对任何表达式执行此操作

enum logic {foo, bar} myEnum
let baz = foo;
let qux = bar;

您不能为实例名称起别名。

SystemVerilog 名称别名

SystemVerilog name alias

system-verilog