无法在 C# 应用程序中为我的线程使用多个处理器组
Unable to use more than one processor group for my threads in a C# app
根据 MSDN documentation and Stephen Toub answer，我的 C# 应用程序应该使用每个处理器组的每个逻辑处理器，因为它是按要求配置的（请参阅下面我的 App.config）。
我 运行 我的应用程序在具有 NUMA 架构的 windows 服务器 2012 上：2 x [cpu Xeon E5-2697 v3，14 个内核，每个内核都激活了超线程] = > 2 x 14 x 2 = 56 个逻辑处理器。
我的应用程序从 "Thread Class" 或 "Parallel.For" 启动 80 个线程，在这两种情况下它只需要 28 个逻辑处理器，全部来自同一个处理器组。
为什么任务调度程序只在一个处理器组上分配我的线程？
我的代码可在 GitHub or the executable could be downloaded at my Home website
我已经在 social.msdn.microsoft.com 上问过这个问题，但没有任何答案。
2015-01-26 更新：我在 connect.microsoft.com
2015-01-30 更新：我添加了 CoreInfo 转储作为附加参考。
2015-01-30 更新：prime95 也会出现问题
仅提供给 select 28 个线程（与 c# 无关）
2015-01-30 更新：我的工具现在显示处理器等更多信息
每个节点的掩码。听起来我无权访问其他节点
（节点我没有运行）
更新 2015-02-02，我们没有在此特定设备上安装 Citrix
服务器（对不起，我错了）
更新 2015-02-02，我们联系了 HP...
2015-02-03更新，添加更多信息到我的程序中显示
每个线程的处理器组和更多的小工具。
更新 2015-02-17，与 HP 开发团队交谈后，我更新了我的答案
反映我学到的东西。 （只想提一下，我得到了 HP 的出色支持）
2015-05-13更新，HP在"Customer Advisory"中确认了该问题
笔记。请参阅此链接文档 ID：c04650594
我将我的 .Net 4.5（或 4.5.1）App.Config 设置为：
<?xml version="1.0" encoding="utf-8"?>
<configuration>
<runtime>
<Thread_UseAllCpuGroups enabled="true"></Thread_UseAllCpuGroups>
<GCCpuGroup enabled="true"></GCCpuGroup>
<gcServer enabled="true"></gcServer>
</runtime>
<startup>
<supportedRuntime version="v4.0" sku=".NETFramework,Version=v4.5.1"/>
</startup>
</configuration>
这是来自 Microsoft 的 CoreInfo 的转储：
Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz
Intel64 Family 6 Model 63 Stepping 2, GenuineIntel
Microcode signature: 00000023
HTT * Hyperthreading enabled
HYPERVISOR - Hypervisor is present
VMX * Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
X64 * Supports 64-bit mode
SMX * Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
NX * Supports no-execute page protection
SMEP * Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB * Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE * Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4a - Supports Streaming SIMDR Extensions 4a
SSE4.1 * Supports Streaming SIMD Extensions 4.1
SSE4.2 * Supports Streaming SIMD Extensions 4.2
AES * Supports AES extensions
AVX * Supports AVX intruction extensions
FMA * Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE * Supports XSAVE/XRSTOR instructions
OSXSAVE * Supports XSETBV/XGETBV instructions
RDRAND * Supports RDRAND instruction
RDSEED - Supports RDSEED instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
BMI1 * Supports bit manipulation extensions 1
BMI2 * Supports bit manipulation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA * Supports prefetch from memory-mapped device
F16C * Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR * Supports MONITOR and MWAIT instructions
MOVBE * Supports MOVBE instruction
ERMSB * Supports Enhanced REP MOVSB/STOSB
PCLMULDQ * Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
LZCNT * Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 * Can write history of 64-bit branch addresses
DS * Implements memory-resident debug buffer
DS-CPL * Supports Debug Store feature with CPL
PCID * Supports PCIDs and settable CR4.PCIDE
INVPCID * Supports INVPCID instruction
PDCM * Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE * Local APIC supports one-shot deadline timer
TSC-INVARIANT * TSC runs at constant rate
xTPR * Supports disabling task priority messages
EIST * Supports Enhanced Intel Speedstep
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 * Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC * Supports x2APIC
CNXT-ID - L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW * Supports PREFETCHW instruction
Maximum implemented CPUID leaves: 0000000F (Basic), 80000008 (Extended).
Logical to Physical Processor Map:
Physical Processor 0 (Hyperthreaded):
**------------------------------------------------------
Physical Processor 1 (Hyperthreaded):
--**----------------------------------------------------
Physical Processor 2 (Hyperthreaded):
----**--------------------------------------------------
Physical Processor 3 (Hyperthreaded):
------**------------------------------------------------
Physical Processor 4 (Hyperthreaded):
--------**----------------------------------------------
Physical Processor 5 (Hyperthreaded):
----------**--------------------------------------------
Physical Processor 6 (Hyperthreaded):
------------**------------------------------------------
Physical Processor 7 (Hyperthreaded):
--------------**----------------------------------------
Physical Processor 8 (Hyperthreaded):
----------------**--------------------------------------
Physical Processor 9 (Hyperthreaded):
------------------**------------------------------------
Physical Processor 10 (Hyperthreaded):
--------------------**----------------------------------
Physical Processor 11 (Hyperthreaded):
----------------------**--------------------------------
Physical Processor 12 (Hyperthreaded):
------------------------**------------------------------
Physical Processor 13 (Hyperthreaded):
--------------------------**----------------------------
Physical Processor 14 (Hyperthreaded):
----------------------------**--------------------------
Physical Processor 15 (Hyperthreaded):
------------------------------**------------------------
Physical Processor 16 (Hyperthreaded):
--------------------------------**----------------------
Physical Processor 17 (Hyperthreaded):
----------------------------------**--------------------
Physical Processor 18 (Hyperthreaded):
------------------------------------**------------------
Physical Processor 19 (Hyperthreaded):
--------------------------------------**----------------
Physical Processor 20 (Hyperthreaded):
----------------------------------------**--------------
Physical Processor 21 (Hyperthreaded):
------------------------------------------**------------
Physical Processor 22 (Hyperthreaded):
--------------------------------------------**----------
Physical Processor 23 (Hyperthreaded):
----------------------------------------------**--------
Physical Processor 24 (Hyperthreaded):
------------------------------------------------**------
Physical Processor 25 (Hyperthreaded):
--------------------------------------------------**----
Physical Processor 26 (Hyperthreaded):
----------------------------------------------------**--
Physical Processor 27 (Hyperthreaded):
------------------------------------------------------**
Logical Processor to Socket Map:
Socket 0:
****************************----------------------------
Socket 1:
----------------------------****************************
Logical Processor to NUMA Node Map:
NUMA Node 0:
****************************----------------------------
NUMA Node 1:
----------------------------****************************
Calculating Cross-NUMA Node Access Cost...
Approximate Cross-NUMA Node Access Cost (relative to fastest):
00 01
00: 1.0 1.1
01: 1.1 1.1
Logical Processor to Cache Map:
Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**------------------------------------------------------
Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**------------------------------------------------------
Unified Cache 0, Level 2, 256 KB, Assoc 8, LineSize 64
**------------------------------------------------------
Unified Cache 1, Level 3, 35 MB, Assoc 20, LineSize 64
****************************----------------------------
Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--**----------------------------------------------------
Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--**----------------------------------------------------
Unified Cache 2, Level 2, 256 KB, Assoc 8, LineSize 64
--**----------------------------------------------------
Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
----**--------------------------------------------------
Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
----**--------------------------------------------------
Unified Cache 3, Level 2, 256 KB, Assoc 8, LineSize 64
----**--------------------------------------------------
Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
------**------------------------------------------------
Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
------**------------------------------------------------
Unified Cache 4, Level 2, 256 KB, Assoc 8, LineSize 64
------**------------------------------------------------
Data Cache 4, Level 1, 32 KB, Assoc 8, LineSize 64
--------**----------------------------------------------
Instruction Cache 4, Level 1, 32 KB, Assoc 8, LineSize 64
--------**----------------------------------------------
Unified Cache 5, Level 2, 256 KB, Assoc 8, LineSize 64
--------**----------------------------------------------
Data Cache 5, Level 1, 32 KB, Assoc 8, LineSize 64
----------**--------------------------------------------
Instruction Cache 5, Level 1, 32 KB, Assoc 8, LineSize 64
----------**--------------------------------------------
Unified Cache 6, Level 2, 256 KB, Assoc 8, LineSize 64
----------**--------------------------------------------
Data Cache 6, Level 1, 32 KB, Assoc 8, LineSize 64
------------**------------------------------------------
Instruction Cache 6, Level 1, 32 KB, Assoc 8, LineSize 64
------------**------------------------------------------
Unified Cache 7, Level 2, 256 KB, Assoc 8, LineSize 64
------------**------------------------------------------
Data Cache 7, Level 1, 32 KB, Assoc 8, LineSize 64
--------------**----------------------------------------
Instruction Cache 7, Level 1, 32 KB, Assoc 8, LineSize 64
--------------**----------------------------------------
Unified Cache 8, Level 2, 256 KB, Assoc 8, LineSize 64
--------------**----------------------------------------
Data Cache 8, Level 1, 32 KB, Assoc 8, LineSize 64
----------------**--------------------------------------
Instruction Cache 8, Level 1, 32 KB, Assoc 8, LineSize 64
----------------**--------------------------------------
Unified Cache 9, Level 2, 256 KB, Assoc 8, LineSize 64
----------------**--------------------------------------
Data Cache 9, Level 1, 32 KB, Assoc 8, LineSize 64
------------------**------------------------------------
Instruction Cache 9, Level 1, 32 KB, Assoc 8, LineSize 64
------------------**------------------------------------
Unified Cache 10, Level 2, 256 KB, Assoc 8, LineSize 64
------------------**------------------------------------
Data Cache 10, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------**----------------------------------
Instruction Cache 10, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------**----------------------------------
Unified Cache 11, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------**----------------------------------
Data Cache 11, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------**--------------------------------
Instruction Cache 11, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------**--------------------------------
Unified Cache 12, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------**--------------------------------
Data Cache 12, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------**------------------------------
Instruction Cache 12, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------**------------------------------
Unified Cache 13, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------**------------------------------
Data Cache 13, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------**----------------------------
Instruction Cache 13, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------**----------------------------
Unified Cache 14, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------**----------------------------
Data Cache 14, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------**--------------------------
Instruction Cache 14, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------**--------------------------
Unified Cache 15, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------**--------------------------
Unified Cache 16, Level 3, 35 MB, Assoc 20, LineSize 64
----------------------------****************************
Data Cache 15, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------**------------------------
Instruction Cache 15, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------**------------------------
Unified Cache 17, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------**------------------------
Data Cache 16, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------**----------------------
Instruction Cache 16, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------**----------------------
Unified Cache 18, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------**----------------------
Data Cache 17, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------**--------------------
Instruction Cache 17, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------**--------------------
Unified Cache 19, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------**--------------------
Data Cache 18, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------**------------------
Instruction Cache 18, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------**------------------
Unified Cache 20, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------**------------------
Data Cache 19, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------**----------------
Instruction Cache 19, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------**----------------
Unified Cache 21, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------------**----------------
Data Cache 20, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------**--------------
Instruction Cache 20, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------**--------------
Unified Cache 22, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------------**--------------
Data Cache 21, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------**------------
Instruction Cache 21, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------**------------
Unified Cache 23, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------------**------------
Data Cache 22, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------**----------
Instruction Cache 22, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------**----------
Unified Cache 24, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------------------**----------
Data Cache 23, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------**--------
Instruction Cache 23, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------**--------
Unified Cache 25, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------------------**--------
Data Cache 24, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------**------
Instruction Cache 24, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------**------
Unified Cache 26, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------------------**------
Data Cache 25, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------------**----
Instruction Cache 25, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------------**----
Unified Cache 27, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------------------------**----
Data Cache 26, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------------**--
Instruction Cache 26, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------------**--
Unified Cache 28, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------------------------**--
Data Cache 27, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------------**
Instruction Cache 27, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------------**
Unified Cache 29, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------------------------**
Logical Processor to Group Map:
Group 0:
****************************----------------------------
Group 1:
----------------------------****************************
这是 MsInfo32 命令转储（有关服务器的信息）：
OS Name Microsoft Windows Server 2012 R2 Standard
Version 6.3.9600 Build 9600
Other OS Description Not Available
OS Manufacturer Microsoft Corporation
System Name EMTP6
System Manufacturer HP
System Model ProLiant DL360 Gen9
System Type x64-based PC
System SKU 755258-B21
Processor Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz, 2597 Mhz, 14 Core(s), 28 Logical Processor(s)
Processor Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz, 2597 Mhz, 14 Core(s), 28 Logical Processor(s)
BIOS Version/Date HP P89, 7/11/2014
SMBIOS Version 2.8
Embedded Controller Version 2.02
BIOS Mode UEFI
Platform Role Enterprise Server
Secure Boot State Off
PCR7 Configuration Not Available
Windows Directory ---removed
System Directory ---removed
Boot Device \Device\HarddiskVolume2
Locale United States
Hardware Abstraction Layer Version = "6.3.9600.17196"
User Name Not Available
Time Zone Eastern Standard Time
Installed Physical Memory (RAM) 256 GB
Total Physical Memory 256 GB
Available Physical Memory 246 GB
Total Virtual Memory 294 GB
Available Virtual Memory 283 GB
Page File Space 38.0 GB
Page File ---removed
Hyper-V - VM Monitor Mode Extensions Yes
Hyper-V - Second Level Address Translation Extensions Yes
Hyper-V - Virtualization Enabled in Firmware Yes
Hyper-V - Data Execution Protection Yes
这是 TaskManager 的屏幕截图和我的程序结果：
或者，如果 Windows 决定在节点 1 上启动它：
另一台服务器的预期行为：
OS Name Microsoft Windows Server 2008 HPC Edition
Version 6.1.7601 Service Pack 1 Build 7601
Other OS Description Not Available
OS Manufacturer Microsoft Corporation
System Name COMPUTE-13-6
System Manufacturer HP
System Model ProLiant DL160 G6
System Type x64-based PC
Processor Intel(R) Xeon(R) CPU X5675 @ 3.07GHz, 3068 Mhz, 6 Core(s), 6 Logical Processor(s)
Processor Intel(R) Xeon(R) CPU X5675 @ 3.07GHz, 3068 Mhz, 6 Core(s), 6 Logical Processor(s)
BIOS Version/Date HP O33, 7/1/2013
SMBIOS Version 2.7
Windows Directory C:\Windows
System Directory C:\Windows\system32
Boot Device \Device\HarddiskVolume1
Locale United States
Hardware Abstraction Layer Version = "6.1.7601.17514"
User Name Not Available
Time Zone Eastern Standard Time
Installed Physical Memory (RAM) 48.0 GB
Total Physical Memory 48.0 GB
Available Physical Memory 40.9 GB
Total Virtual Memory 96.0 GB
Available Virtual Memory 88.4 GB
Page File Space 48.0 GB
Page File C:\pagefile.sys
注意：我认为我们通过更改 bios 中的 "Interleaved Memory" 参数解决了这个问题。但我给了我们奇怪的结果。根据 Microsoft Technet，我们将 BIOS 设置回 "NON-Interleaved memory"**（OS 需要将系统视为 NUMA）。
这个程序会不会死锁？我无法确定您的线程池是否已完全扩展。
using System.Linq;
using System.Threading;
using System.Threading.Tasks;
class Program
{
static void Main(string[] args)
{
var threads = 100;
int workerThreads, completionPortThreads;
ThreadPool.GetMaxThreads(out workerThreads, out completionPortThreads);
ThreadPool.SetMaxThreads(threads, completionPortThreads);
ThreadPool.GetMinThreads(out workerThreads, out completionPortThreads);
ThreadPool.SetMinThreads(threads, completionPortThreads);
var ce = new CountdownEvent(threads + 1);
Enumerable.
Range(0, threads).
Select(xs => Task.Factory.StartNew(() => { ce.Signal(); ce.Wait(); })).
ToArray();
ce.Signal();
ce.Wait();
}
}
尝试将您的代码设置为构建“优化代码”并将目标平台设置为“x64”。
（在 80 个内核的服务器上，你的代码对我有用）
这是我们的 MsInfo32：
OS Name Microsoft Windows Server 2012 R2 Standard
Version 6.3.9600 Build 9600
Other OS Description Not Available
OS Manufacturer Microsoft Corporation
System Manufacturer IBM
System Model System x3850 X5
System Type x64-based PC
System SKU
Processor Intel(R) Xeon(R) CPU E7- 4870 @ 2.40GHz, 2395 Mhz, 10
Core(s), 20 Logical Processor(s)
Processor Intel(R) Xeon(R) CPU E7- 4870 @ 2.40GHz, 2395 Mhz, 10
Core(s), 20 Logical Processor(s)
处理器 Intel(R) Xeon(R) CPU E7- 4870 @ 2.40GHz，2395 Mhz，10 个核心，20 个逻辑处理器
处理器 Intel(R) Xeon(R) CPU E7- 4870 @ 2.40GHz，2395 Mhz，10 个核心，20 个逻辑处理器
BIOS Version/Date IBM Corp. -[G0E179BUS-1.79]-, 28-07-2013
SMBIOS Version 2.7
Embedded Controller Version 255.255
BIOS Mode UEFI
BaseBoard Manufacturer IBM
BaseBoard Model Not Available
BaseBoard Name Base Board
Platform Role Enterprise Server
Secure Boot State Unsupported
PCR7 Configuration Not Available
Hardware Abstraction Layer Version = "6.3.9600.17031"
User Name Not Available
Time Zone Romance Standard Time
Installed Physical Memory (RAM) 128 GB
Total Physical Memory 128 GB
Available Physical Memory 53,0 GB
Total Virtual Memory 147 GB
Available Virtual Memory 67,7 GB
Hyper-V - VM Monitor Mode Extensions Yes
Hyper-V - Second Level Address Translation Extensions Yes
Hyper-V - Virtualization Enabled in Firmware Yes
Hyper-V - Data Execution Protection Yes
并且你应该确保没有工作限制。
https://msdn.microsoft.com/en-us/library/windows/desktop/ms684147(v=vs.85).aspx
您可以通过 Process Explorer 查看
https://technet.microsoft.com/en-us/sysinternals/bb896653.aspx
该错误已被新的（尚未发布的）HP Bios（在撰写本文时）修复。
新的 Bios（针对 HP Proliant DL360 和 DL380 Gen9）引入了一个新设置："NUMA Group Size Optimization" 可以选择 [Clustered - default] 或 [Flat]。 HP 说要将其设置为平坦。
由于服务器可用性，此答案的截图部分已在 DL380 而不是 DL360 上进行。但我希望在 DL360 上有同样的行为。问题消失了，我们只有一组。
据我所知，OS 与 BIOS 通信以了解 CPU(s) 配置。 Bios 在 OS 如何呈现可供应用程序使用的逻辑处理器（处理器组、亲和性等）方面发挥着重要作用。
关于 Microsoft 文档 Supporting Systems That Have More Than 64 Processors and Processor Groups it is clearly stated that more than one processor group will only be created when the Logical Processor (LC) count is >64. On our server (56 LC) with Numa Architecture set to "Clustered" we had 2 processor groups. A hardware engineer working at HP Bios dev team explained me that when set to "Clustered", the Bios is fooling Windows by padding the real number of logical processor to 72 Logical Processor (the max number of Logical Processor for the E5 v3 Family)。在我们的DL360中，LC的真实数量是56个。这就是为什么我们添加 2 个组而不是 1 个组的原因。Microsoft 文档似乎是准确的。我个人认为最好尽可能为每个 numa 节点创建 1 个组，但在我们的例子中，存在一个错误。当 HP Bios 设置设置为 Clustered（默认）时，很难在 HP 或 Microsoft 之间知道有什么问题，但 Microsoft 似乎不支持该选项，这似乎会导致我们的问题。
在适用于 DL360 和 DL380 的 HP Bios 上，Bios 配置 "Numa Configuration" 设置为 "Clustered"（默认）将创建 2 个组，尽管只有 56 个逻辑处理器（超线程时）。结果是任何应用程序一次只能看到一个处理器。也可能是由于惠普通过填充虚假数量的逻辑处理器来欺骗 Windows。听起来微软并不希望如此。我们的 C# 应用程序不能 运行 这两个组。很难将惠普做出他们无法预料的事情的行为归咎于微软。也许有一天我们会看到，Windows 在 LC <= 64 时支持许多组。
关于 Prime95。这个 CPU 压力测试软件有很好的 documentation on Wikipedia，清楚地表明它只会加载到一个处理器组（在限制部分）。
根据 MSDN documentation and Stephen Toub answer，我的 C# 应用程序应该使用每个处理器组的每个逻辑处理器，因为它是按要求配置的（请参阅下面我的 App.config）。
我 运行 我的应用程序在具有 NUMA 架构的 windows 服务器 2012 上：2 x [cpu Xeon E5-2697 v3，14 个内核，每个内核都激活了超线程] = > 2 x 14 x 2 = 56 个逻辑处理器。
我的应用程序从 "Thread Class" 或 "Parallel.For" 启动 80 个线程，在这两种情况下它只需要 28 个逻辑处理器，全部来自同一个处理器组。
为什么任务调度程序只在一个处理器组上分配我的线程？
我的代码可在 GitHub or the executable could be downloaded at my Home website
我已经在 social.msdn.microsoft.com 上问过这个问题，但没有任何答案。
2015-01-26 更新：我在 connect.microsoft.com
报告了一个错误
2015-01-30 更新：我添加了 CoreInfo 转储作为附加参考。
2015-01-30 更新：prime95 也会出现问题 仅提供给 select 28 个线程（与 c# 无关）
2015-01-30 更新：我的工具现在显示处理器等更多信息 每个节点的掩码。听起来我无权访问其他节点 （节点我没有运行）
更新 2015-02-02，我们没有在此特定设备上安装 Citrix 服务器（对不起，我错了）
更新 2015-02-02，我们联系了 HP...
2015-02-03更新，添加更多信息到我的程序中显示 每个线程的处理器组和更多的小工具。
更新 2015-02-17，与 HP 开发团队交谈后，我更新了我的答案 反映我学到的东西。 （只想提一下，我得到了 HP 的出色支持）
2015-05-13更新，HP在"Customer Advisory"中确认了该问题 笔记。请参阅此链接文档 ID：c04650594
我将我的 .Net 4.5（或 4.5.1）App.Config 设置为：
<?xml version="1.0" encoding="utf-8"?>
<configuration>
<runtime>
<Thread_UseAllCpuGroups enabled="true"></Thread_UseAllCpuGroups>
<GCCpuGroup enabled="true"></GCCpuGroup>
<gcServer enabled="true"></gcServer>
</runtime>
<startup>
<supportedRuntime version="v4.0" sku=".NETFramework,Version=v4.5.1"/>
</startup>
</configuration>
这是来自 Microsoft 的 CoreInfo 的转储：
Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz
Intel64 Family 6 Model 63 Stepping 2, GenuineIntel
Microcode signature: 00000023
HTT * Hyperthreading enabled
HYPERVISOR - Hypervisor is present
VMX * Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
X64 * Supports 64-bit mode
SMX * Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
NX * Supports no-execute page protection
SMEP * Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB * Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE * Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4a - Supports Streaming SIMDR Extensions 4a
SSE4.1 * Supports Streaming SIMD Extensions 4.1
SSE4.2 * Supports Streaming SIMD Extensions 4.2
AES * Supports AES extensions
AVX * Supports AVX intruction extensions
FMA * Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE * Supports XSAVE/XRSTOR instructions
OSXSAVE * Supports XSETBV/XGETBV instructions
RDRAND * Supports RDRAND instruction
RDSEED - Supports RDSEED instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
BMI1 * Supports bit manipulation extensions 1
BMI2 * Supports bit manipulation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA * Supports prefetch from memory-mapped device
F16C * Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR * Supports MONITOR and MWAIT instructions
MOVBE * Supports MOVBE instruction
ERMSB * Supports Enhanced REP MOVSB/STOSB
PCLMULDQ * Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
LZCNT * Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 * Can write history of 64-bit branch addresses
DS * Implements memory-resident debug buffer
DS-CPL * Supports Debug Store feature with CPL
PCID * Supports PCIDs and settable CR4.PCIDE
INVPCID * Supports INVPCID instruction
PDCM * Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE * Local APIC supports one-shot deadline timer
TSC-INVARIANT * TSC runs at constant rate
xTPR * Supports disabling task priority messages
EIST * Supports Enhanced Intel Speedstep
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 * Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC * Supports x2APIC
CNXT-ID - L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW * Supports PREFETCHW instruction
Maximum implemented CPUID leaves: 0000000F (Basic), 80000008 (Extended).
Logical to Physical Processor Map:
Physical Processor 0 (Hyperthreaded):
**------------------------------------------------------
Physical Processor 1 (Hyperthreaded):
--**----------------------------------------------------
Physical Processor 2 (Hyperthreaded):
----**--------------------------------------------------
Physical Processor 3 (Hyperthreaded):
------**------------------------------------------------
Physical Processor 4 (Hyperthreaded):
--------**----------------------------------------------
Physical Processor 5 (Hyperthreaded):
----------**--------------------------------------------
Physical Processor 6 (Hyperthreaded):
------------**------------------------------------------
Physical Processor 7 (Hyperthreaded):
--------------**----------------------------------------
Physical Processor 8 (Hyperthreaded):
----------------**--------------------------------------
Physical Processor 9 (Hyperthreaded):
------------------**------------------------------------
Physical Processor 10 (Hyperthreaded):
--------------------**----------------------------------
Physical Processor 11 (Hyperthreaded):
----------------------**--------------------------------
Physical Processor 12 (Hyperthreaded):
------------------------**------------------------------
Physical Processor 13 (Hyperthreaded):
--------------------------**----------------------------
Physical Processor 14 (Hyperthreaded):
----------------------------**--------------------------
Physical Processor 15 (Hyperthreaded):
------------------------------**------------------------
Physical Processor 16 (Hyperthreaded):
--------------------------------**----------------------
Physical Processor 17 (Hyperthreaded):
----------------------------------**--------------------
Physical Processor 18 (Hyperthreaded):
------------------------------------**------------------
Physical Processor 19 (Hyperthreaded):
--------------------------------------**----------------
Physical Processor 20 (Hyperthreaded):
----------------------------------------**--------------
Physical Processor 21 (Hyperthreaded):
------------------------------------------**------------
Physical Processor 22 (Hyperthreaded):
--------------------------------------------**----------
Physical Processor 23 (Hyperthreaded):
----------------------------------------------**--------
Physical Processor 24 (Hyperthreaded):
------------------------------------------------**------
Physical Processor 25 (Hyperthreaded):
--------------------------------------------------**----
Physical Processor 26 (Hyperthreaded):
----------------------------------------------------**--
Physical Processor 27 (Hyperthreaded):
------------------------------------------------------**
Logical Processor to Socket Map:
Socket 0:
****************************----------------------------
Socket 1:
----------------------------****************************
Logical Processor to NUMA Node Map:
NUMA Node 0:
****************************----------------------------
NUMA Node 1:
----------------------------****************************
Calculating Cross-NUMA Node Access Cost...
Approximate Cross-NUMA Node Access Cost (relative to fastest):
00 01
00: 1.0 1.1
01: 1.1 1.1
Logical Processor to Cache Map:
Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**------------------------------------------------------
Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**------------------------------------------------------
Unified Cache 0, Level 2, 256 KB, Assoc 8, LineSize 64
**------------------------------------------------------
Unified Cache 1, Level 3, 35 MB, Assoc 20, LineSize 64
****************************----------------------------
Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--**----------------------------------------------------
Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--**----------------------------------------------------
Unified Cache 2, Level 2, 256 KB, Assoc 8, LineSize 64
--**----------------------------------------------------
Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
----**--------------------------------------------------
Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
----**--------------------------------------------------
Unified Cache 3, Level 2, 256 KB, Assoc 8, LineSize 64
----**--------------------------------------------------
Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
------**------------------------------------------------
Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
------**------------------------------------------------
Unified Cache 4, Level 2, 256 KB, Assoc 8, LineSize 64
------**------------------------------------------------
Data Cache 4, Level 1, 32 KB, Assoc 8, LineSize 64
--------**----------------------------------------------
Instruction Cache 4, Level 1, 32 KB, Assoc 8, LineSize 64
--------**----------------------------------------------
Unified Cache 5, Level 2, 256 KB, Assoc 8, LineSize 64
--------**----------------------------------------------
Data Cache 5, Level 1, 32 KB, Assoc 8, LineSize 64
----------**--------------------------------------------
Instruction Cache 5, Level 1, 32 KB, Assoc 8, LineSize 64
----------**--------------------------------------------
Unified Cache 6, Level 2, 256 KB, Assoc 8, LineSize 64
----------**--------------------------------------------
Data Cache 6, Level 1, 32 KB, Assoc 8, LineSize 64
------------**------------------------------------------
Instruction Cache 6, Level 1, 32 KB, Assoc 8, LineSize 64
------------**------------------------------------------
Unified Cache 7, Level 2, 256 KB, Assoc 8, LineSize 64
------------**------------------------------------------
Data Cache 7, Level 1, 32 KB, Assoc 8, LineSize 64
--------------**----------------------------------------
Instruction Cache 7, Level 1, 32 KB, Assoc 8, LineSize 64
--------------**----------------------------------------
Unified Cache 8, Level 2, 256 KB, Assoc 8, LineSize 64
--------------**----------------------------------------
Data Cache 8, Level 1, 32 KB, Assoc 8, LineSize 64
----------------**--------------------------------------
Instruction Cache 8, Level 1, 32 KB, Assoc 8, LineSize 64
----------------**--------------------------------------
Unified Cache 9, Level 2, 256 KB, Assoc 8, LineSize 64
----------------**--------------------------------------
Data Cache 9, Level 1, 32 KB, Assoc 8, LineSize 64
------------------**------------------------------------
Instruction Cache 9, Level 1, 32 KB, Assoc 8, LineSize 64
------------------**------------------------------------
Unified Cache 10, Level 2, 256 KB, Assoc 8, LineSize 64
------------------**------------------------------------
Data Cache 10, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------**----------------------------------
Instruction Cache 10, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------**----------------------------------
Unified Cache 11, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------**----------------------------------
Data Cache 11, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------**--------------------------------
Instruction Cache 11, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------**--------------------------------
Unified Cache 12, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------**--------------------------------
Data Cache 12, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------**------------------------------
Instruction Cache 12, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------**------------------------------
Unified Cache 13, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------**------------------------------
Data Cache 13, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------**----------------------------
Instruction Cache 13, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------**----------------------------
Unified Cache 14, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------**----------------------------
Data Cache 14, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------**--------------------------
Instruction Cache 14, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------**--------------------------
Unified Cache 15, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------**--------------------------
Unified Cache 16, Level 3, 35 MB, Assoc 20, LineSize 64
----------------------------****************************
Data Cache 15, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------**------------------------
Instruction Cache 15, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------**------------------------
Unified Cache 17, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------**------------------------
Data Cache 16, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------**----------------------
Instruction Cache 16, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------**----------------------
Unified Cache 18, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------**----------------------
Data Cache 17, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------**--------------------
Instruction Cache 17, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------**--------------------
Unified Cache 19, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------**--------------------
Data Cache 18, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------**------------------
Instruction Cache 18, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------**------------------
Unified Cache 20, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------**------------------
Data Cache 19, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------**----------------
Instruction Cache 19, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------**----------------
Unified Cache 21, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------------**----------------
Data Cache 20, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------**--------------
Instruction Cache 20, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------**--------------
Unified Cache 22, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------------**--------------
Data Cache 21, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------**------------
Instruction Cache 21, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------**------------
Unified Cache 23, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------------**------------
Data Cache 22, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------**----------
Instruction Cache 22, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------**----------
Unified Cache 24, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------------------**----------
Data Cache 23, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------**--------
Instruction Cache 23, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------**--------
Unified Cache 25, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------------------**--------
Data Cache 24, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------**------
Instruction Cache 24, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------**------
Unified Cache 26, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------------------**------
Data Cache 25, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------------**----
Instruction Cache 25, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------------**----
Unified Cache 27, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------------------------**----
Data Cache 26, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------------**--
Instruction Cache 26, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------------**--
Unified Cache 28, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------------------------**--
Data Cache 27, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------------**
Instruction Cache 27, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------------**
Unified Cache 29, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------------------------**
Logical Processor to Group Map:
Group 0:
****************************----------------------------
Group 1:
----------------------------****************************
这是 MsInfo32 命令转储（有关服务器的信息）：
OS Name Microsoft Windows Server 2012 R2 Standard
Version 6.3.9600 Build 9600
Other OS Description Not Available
OS Manufacturer Microsoft Corporation
System Name EMTP6
System Manufacturer HP
System Model ProLiant DL360 Gen9
System Type x64-based PC
System SKU 755258-B21
Processor Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz, 2597 Mhz, 14 Core(s), 28 Logical Processor(s)
Processor Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz, 2597 Mhz, 14 Core(s), 28 Logical Processor(s)
BIOS Version/Date HP P89, 7/11/2014
SMBIOS Version 2.8
Embedded Controller Version 2.02
BIOS Mode UEFI
Platform Role Enterprise Server
Secure Boot State Off
PCR7 Configuration Not Available
Windows Directory ---removed
System Directory ---removed
Boot Device \Device\HarddiskVolume2
Locale United States
Hardware Abstraction Layer Version = "6.3.9600.17196"
User Name Not Available
Time Zone Eastern Standard Time
Installed Physical Memory (RAM) 256 GB
Total Physical Memory 256 GB
Available Physical Memory 246 GB
Total Virtual Memory 294 GB
Available Virtual Memory 283 GB
Page File Space 38.0 GB
Page File ---removed
Hyper-V - VM Monitor Mode Extensions Yes
Hyper-V - Second Level Address Translation Extensions Yes
Hyper-V - Virtualization Enabled in Firmware Yes
Hyper-V - Data Execution Protection Yes
这是 TaskManager 的屏幕截图和我的程序结果：
或者，如果 Windows 决定在节点 1 上启动它：
另一台服务器的预期行为：
OS Name Microsoft Windows Server 2008 HPC Edition
Version 6.1.7601 Service Pack 1 Build 7601
Other OS Description Not Available
OS Manufacturer Microsoft Corporation
System Name COMPUTE-13-6
System Manufacturer HP
System Model ProLiant DL160 G6
System Type x64-based PC
Processor Intel(R) Xeon(R) CPU X5675 @ 3.07GHz, 3068 Mhz, 6 Core(s), 6 Logical Processor(s)
Processor Intel(R) Xeon(R) CPU X5675 @ 3.07GHz, 3068 Mhz, 6 Core(s), 6 Logical Processor(s)
BIOS Version/Date HP O33, 7/1/2013
SMBIOS Version 2.7
Windows Directory C:\Windows
System Directory C:\Windows\system32
Boot Device \Device\HarddiskVolume1
Locale United States
Hardware Abstraction Layer Version = "6.1.7601.17514"
User Name Not Available
Time Zone Eastern Standard Time
Installed Physical Memory (RAM) 48.0 GB
Total Physical Memory 48.0 GB
Available Physical Memory 40.9 GB
Total Virtual Memory 96.0 GB
Available Virtual Memory 88.4 GB
Page File Space 48.0 GB
Page File C:\pagefile.sys
注意：我认为我们通过更改 bios 中的 "Interleaved Memory" 参数解决了这个问题。但我给了我们奇怪的结果。根据 Microsoft Technet，我们将 BIOS 设置回 "NON-Interleaved memory"**（OS 需要将系统视为 NUMA）。
这个程序会不会死锁？我无法确定您的线程池是否已完全扩展。
using System.Linq;
using System.Threading;
using System.Threading.Tasks;
class Program
{
static void Main(string[] args)
{
var threads = 100;
int workerThreads, completionPortThreads;
ThreadPool.GetMaxThreads(out workerThreads, out completionPortThreads);
ThreadPool.SetMaxThreads(threads, completionPortThreads);
ThreadPool.GetMinThreads(out workerThreads, out completionPortThreads);
ThreadPool.SetMinThreads(threads, completionPortThreads);
var ce = new CountdownEvent(threads + 1);
Enumerable.
Range(0, threads).
Select(xs => Task.Factory.StartNew(() => { ce.Signal(); ce.Wait(); })).
ToArray();
ce.Signal();
ce.Wait();
}
}
尝试将您的代码设置为构建“优化代码”并将目标平台设置为“x64”。 （在 80 个内核的服务器上，你的代码对我有用）
这是我们的 MsInfo32：
OS Name Microsoft Windows Server 2012 R2 Standard
Version 6.3.9600 Build 9600
Other OS Description Not Available
OS Manufacturer Microsoft Corporation
System Manufacturer IBM
System Model System x3850 X5
System Type x64-based PC
System SKU
Processor Intel(R) Xeon(R) CPU E7- 4870 @ 2.40GHz, 2395 Mhz, 10 Core(s), 20 Logical Processor(s)
Processor Intel(R) Xeon(R) CPU E7- 4870 @ 2.40GHz, 2395 Mhz, 10 Core(s), 20 Logical Processor(s)
处理器 Intel(R) Xeon(R) CPU E7- 4870 @ 2.40GHz，2395 Mhz，10 个核心，20 个逻辑处理器
处理器 Intel(R) Xeon(R) CPU E7- 4870 @ 2.40GHz，2395 Mhz，10 个核心，20 个逻辑处理器
BIOS Version/Date IBM Corp. -[G0E179BUS-1.79]-, 28-07-2013
SMBIOS Version 2.7
Embedded Controller Version 255.255
BIOS Mode UEFI
BaseBoard Manufacturer IBM
BaseBoard Model Not Available
BaseBoard Name Base Board
Platform Role Enterprise Server
Secure Boot State Unsupported
PCR7 Configuration Not Available
Hardware Abstraction Layer Version = "6.3.9600.17031"
User Name Not Available
Time Zone Romance Standard Time
Installed Physical Memory (RAM) 128 GB
Total Physical Memory 128 GB
Available Physical Memory 53,0 GB
Total Virtual Memory 147 GB
Available Virtual Memory 67,7 GB
Hyper-V - VM Monitor Mode Extensions Yes
Hyper-V - Second Level Address Translation Extensions Yes
Hyper-V - Virtualization Enabled in Firmware Yes
Hyper-V - Data Execution Protection Yes
并且你应该确保没有工作限制。
https://msdn.microsoft.com/en-us/library/windows/desktop/ms684147(v=vs.85).aspx
您可以通过 Process Explorer 查看
https://technet.microsoft.com/en-us/sysinternals/bb896653.aspx
该错误已被新的（尚未发布的）HP Bios（在撰写本文时）修复。
新的 Bios（针对 HP Proliant DL360 和 DL380 Gen9）引入了一个新设置："NUMA Group Size Optimization" 可以选择 [Clustered - default] 或 [Flat]。 HP 说要将其设置为平坦。
由于服务器可用性，此答案的截图部分已在 DL380 而不是 DL360 上进行。但我希望在 DL360 上有同样的行为。问题消失了，我们只有一组。
据我所知，OS 与 BIOS 通信以了解 CPU(s) 配置。 Bios 在 OS 如何呈现可供应用程序使用的逻辑处理器（处理器组、亲和性等）方面发挥着重要作用。
关于 Microsoft 文档 Supporting Systems That Have More Than 64 Processors and Processor Groups it is clearly stated that more than one processor group will only be created when the Logical Processor (LC) count is >64. On our server (56 LC) with Numa Architecture set to "Clustered" we had 2 processor groups. A hardware engineer working at HP Bios dev team explained me that when set to "Clustered", the Bios is fooling Windows by padding the real number of logical processor to 72 Logical Processor (the max number of Logical Processor for the E5 v3 Family)。在我们的DL360中，LC的真实数量是56个。这就是为什么我们添加 2 个组而不是 1 个组的原因。Microsoft 文档似乎是准确的。我个人认为最好尽可能为每个 numa 节点创建 1 个组，但在我们的例子中，存在一个错误。当 HP Bios 设置设置为 Clustered（默认）时，很难在 HP 或 Microsoft 之间知道有什么问题，但 Microsoft 似乎不支持该选项，这似乎会导致我们的问题。
在适用于 DL360 和 DL380 的 HP Bios 上，Bios 配置 "Numa Configuration" 设置为 "Clustered"（默认）将创建 2 个组，尽管只有 56 个逻辑处理器（超线程时）。结果是任何应用程序一次只能看到一个处理器。也可能是由于惠普通过填充虚假数量的逻辑处理器来欺骗 Windows。听起来微软并不希望如此。我们的 C# 应用程序不能 运行 这两个组。很难将惠普做出他们无法预料的事情的行为归咎于微软。也许有一天我们会看到，Windows 在 LC <= 64 时支持许多组。
关于 Prime95。这个 CPU 压力测试软件有很好的 documentation on Wikipedia，清楚地表明它只会加载到一个处理器组（在限制部分）。