How do I fix "Error: Illegal range in part select"?

Question

bit[2:0]  size;
bit[2:0]  num;
bit[59:0] data;
data = 60'h12345;
num = 3'h1;
size = 3'h1;

data = {(num+1){data[(size+1)*10-1:0]}};

////Error-[IRIPS] Illegal range in part select

////Warning-[WUIMCM] Unknown in multiconcat multiplier

我该如何解决这些问题？

Answer 1

SystemVerilog 不允许操作数中的可变宽度。您需要为 data 变量的 select 部分创建掩码，并且需要使用 aa for 循环进行复制。

bit [59:0] data_select = data;

data_select &= (61'b1 << (size+1)*10) - 1;
for(int i=0;i<num+1;i++) begin
   data <<= (size+1)*10;
   data |= data_select;
end

How do I fix "Error: Illegal range in part select"?

How do I fix "Error: Illegal range in part select"?

system-verilog