我如何简化这些重复的 make 目标？

Question

考虑这些目标：

test/masterfiles/efl_data/efl_class_cmd_regcmp.json: \
  test/masterfiles/efl_data/efl_class_cmd_regcmp.csv
   $(CSVTOJSON) -b efl_class_cmd_regcmp < $< > $@

test/masterfiles/efl_data/efl_class_returnszero.json: \
  test/masterfiles/efl_data/efl_class_returnszero.csv
   $(CSVTOJSON) -b efl_class_returnszero < $< > $@

test/masterfiles/efl_data/efl_class_expression.json: \
  test/masterfiles/efl_data/efl_class_expression.csv
   $(CSVTOJSON) -b efl_class_expression < $< > $@

模式efl_class_some_word在目标、依赖项和制作目标的配方中重复。我该怎么做才能将这些规则缩减为一条规则？那么正常使用%、$@、@<似乎都不适用。

Answer 1

编写模式规则：

EFL_PARTS = cmd_regcmp returnszero expression

EFL_DIR = test/masterfiles/efl_data

$(EFL_DIR)/%.json: $(EFL_DIR)/%.csv
        $(CSVTOJSON) -b $* < $< > $@

all: $(patsubst %,$(EFL_DIR)/efl_class_%.json,$(EFL_PARTS))
.PHONY: all

我如何简化这些重复的 make 目标？

How do I simplify these repetitive make targets?

makefile

gnu-make