SystemVerilog Verilog 中的非数组移位运算符？

Question

我运行在 SystemVerilog sim 中进入这一行，我用谷歌搜索了一下，但我不确定它在做什么：

data_w = { >> 32 { { >> { data } } } };

任何澄清将不胜感激！谢谢！

Answer 1

这叫做流式传输。它存在于 SystemVerilog 中；不是 Verilog。有关完整说明，请参阅 IEEE Std 1800-2012 § 11.4.14 流式运算符 (pack/unpack)

The slice_size determines the size of each block, measured in bits. If a slice_size is not specified, the default is 1. If specified, it may be a constant integral expression or a simple type. If a type is used, the block size shall be the number of bits in that type. If a constant integral expression is used, it shall be an error for the value of the expression to be zero or negative.

The stream_operator << or >> determines the order in which blocks of data are streamed: >> causes blocks of data to be streamed in left-to-right order, while << causes blocks of data to be streamed in right-to-left order. Left-to-right streaming using >> shall cause the slice_size to be ignored and no re-ordering performed. Right-to-left streaming using << shall reverse the order of blocks in the stream, preserving the order of bits within each block. For right-to-left streaming using <<, the stream is sliced into blocks with the specified number of bits, starting with the right-most bit. If as a result of slicing the last (left-most) block has fewer bits than the block size, the last block has the size of the remaining bits; there is no padding or truncation.

示例形式 IEEE Std 1800-2012 § 11.4.14.2 通用流的重新排序

int j = { "A", "B", "C", "D" };
{ >> {j}} // generates stream "A" "B" "C" "D"
{ << byte {j}} // generates stream "D" "C" "B" "A" (little endian)
{ << 16 {j}} // generates stream "C" "D" "A" "B"
{ << { 8'b0011_0101 }} // generates stream 'b1010_1100 (bit reverse)
{ << 4 { 6'b11_0101 }} // generates stream 'b0101_11
{ >> 4 { 6'b11_0101 }} // generates stream 'b1101_01 (same)
{ << 2 { { << { 4'b1101 }} }} // generates stream 'b1110

SystemVerilog Verilog 中的非数组移位运算符？

Unarray shift operator in SystemVerilog Verilog?

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