verilog 语法错误（HDLCompiler:806）

Question

我是 Verilog 的新手，我不断收到这些编译错误。我用谷歌搜索了错误，但没有得到答案。这是我的代码和错误。

always @(*) begin
     //seed=32'habcd123cd;//assigning seed
     if(posedge axi_clk & first[0]) begin
          load_seed=1'b1;
     end

     if(load_seed) begin
          first[1]=1'b1;
     end

     if(negedge axi_clk & first[1]) begin
          load_seed=1'b0;
          first=2'b00;
     end
 end

我的错误

ERROR:HDLCompiler:806 - "K:/final project/codes/v2/input_arbiter.v" Line 252: Syntax error near "posedge".
ERROR:HDLCompiler:806 - "K:/final project/codes/v2/input_arbiter.v" Line 258: Syntax error near "negedge".
ERROR:HDLCompiler:598 - "K:/final project/codes/v2/input_arbiter.v" Line 46: Module ignored due to previous errors.

Answer 1

您使用 posedge/negedge 的方式有误。这些关键字应该用在 always 块的敏感列表中，例如：

always @(posedge clk)

或

always @(negedge clk)

always @(*)用于描述组合逻辑，或逻辑门。您要实现的是时序逻辑。

你也应该知道（请参考this主题）

when you assign to a register in an edge-sensitive always block, you're defining a flip-flop. FPGAs do not have flip-flops that can trigger on both edges of a clock. That's why you need two separate always blocks, one for each edge of the clock, and then figure out a way to combine the outputs of the two blocks without creating glitches.

verilog 语法错误（HDLCompiler:806）

verilog Syntax error(HDLCompiler:806)

verilog