Verilog 赋值导致左轴 'x' 而右轴具有有效值

Question

我被这个问题卡了两天了，一直无法解决。在此 verilog 加密代码中，我在这一行中有一个分配：sumOut = out，当我尝试使用 ModelSim 对其进行调试时，网络 out 具有有效值，但 sumOut 保持未定义 x。这是代码：

`include "adder.v"

module processData(dataOut0, dataOut1, dataIn0, dataIn1, key0, key1, key2, key3, sumIn, sumOut, delta, clk, rst, finish);

output reg [1:32] dataOut0, dataOut1, sumOut;
output reg finish;

input [1:32] dataIn0, dataIn1, key0, key1, key2, key3, sumIn, delta;
input clk, rst;

reg [1:32] in1, in2, first, second, third, tsum;
wire [1:32] out;

integer cnt;

adder add(out, in1, in2);

always @(posedge clk or negedge rst)
begin
    if(!rst)
    begin
        cnt = 0;
        finish = 0;
        //sumOut = 0;
    end
    else
    begin
        if(cnt == 0)
        begin
            in1 = sumIn; 
            in2 = delta;
            sumOut = out;
            cnt = cnt + 1;
        end
        else if(cnt == 1)
        begin
            in1 = dataIn1 << 4;
            in2 = key0;
            first = out;
            cnt = cnt + 1;
        end
        else if(cnt == 2)
        begin
            in1 = dataIn1; 
            in2 = sumOut;
            second = out;
            cnt = cnt + 1;
        end
        else if(cnt == 3)
        begin
            in1 = dataIn1 >> 5;
            in2 = key1;
            third = out;
            cnt = cnt + 1;
        end
        else if(cnt == 4)
        begin
            tsum = first ^ second ^ third;
            cnt = cnt + 1;
        end
        else if(cnt == 5)
        begin 
            in1 = tsum;
            in2 = dataIn0;
            dataOut0 = out;
            cnt = cnt + 1;
        end
        else if(cnt == 6)
        begin
            in1 = dataOut0 << 4;
            in2 = key2;
            first = out;
            cnt = cnt + 1;
        end
        else if(cnt == 7)
        begin
            in1 = dataOut0; 
            in2 = sumOut;
            second = out;
            cnt = cnt + 1;
        end
        else if(cnt == 8)
        begin
            in1 = dataOut0 >> 5;
            in2 = key3;
            third = out;
            cnt = cnt + 1;
        end
        else if(cnt == 9)
        begin
            tsum = first ^ second ^ third;
            cnt = cnt + 1;
        end
        else if(cnt == 10)
        begin 
            in1 = tsum;
            in2 = dataIn1;
            dataOut1 = out;
            cnt = cnt + 1;
        end
        else if(cnt == 11)
        begin
            finish = 1;
        end
    end
end
endmodule

Answer 1

只是想指出，在您的重置语句中 sumOut = 0 已被注释掉，因此它不会重置寄存器。另一个 if else 可能已经结束工作，因为 else 默认执行。因为上面的代码中只有 else if 而没有 else 不在乎设置。

Answer 2

我通过进行以下更改解决了我的问题。似乎直到下一个时钟触发后才开始分配。

if(cnt == 0)
begin
    in1 <= sumIn; 
    in2 <= delta;
    cnt <= cnt + 1;
end
else if(cnt == 1)
begin
    sumOut <= out;
    cnt <= cnt + 1;
end

Verilog 赋值导致左轴 'x' 而右轴具有有效值

Verilog assignment result in 'x' in LHS while RHS has a valid value

encryption

verilog