连接到多个驱动程序的信号结果植入

Question

我一直在尝试实现一个简单的 verilog 程序，但我始终将运行分为两个错误，我似乎可以找到解决方案。我收到的两个错误是：

1. Line 21: Empty module <AddOrSubtractThenSelectAndDecodedInto7SegmentsDisplay> remains a black box. 

2. Line 40: Signal Result[3] in unit AddOrSubtractThenSelectAndDecodedInto7SegmentsDisplay is connected to following multiple drivers:

Driver 0: output signal Result[3] of instance Latch (Result[3]).
Driver 1: output signal Result[3] of instance Latch (_i000011).
Driver 0: output signal Result[2] of instance Latch (Result[2]).
Driver 1: output signal Result[2] of instance Latch (_i000012).
Driver 0: output signal Result[1] of instance Latch (Result[1]).
Driver 1: output signal Result[1] of instance Latch (_i000013).
Driver 0: output signal Result[0] of instance Latch (Result[0]).
Driver 1: output signal Result[0] of instance Latch (_i000014).
Module AddOrSubtractThenSelectAndDecodedInto7SegmentsDisplay remains a blackbox, due to errors in its contents

我试图在提问之前找到解决方案，但找不到适合我的问题的解决方案。所以我的问题是：为什么会发生这种情况，解决这个问题的最佳解决方案是什么？

这是我的 verilog 代码（没有测试台）：

module AddOrSubtractThenSelectAndDecodedInto7SegmentsDisplay(A,B,S,Result,OF,Display);

// Inputs A,B,S
input [3:0] A;
input [3:0] B;
input [1:0] S;

// Outputs OF,Result,Display
output reg [6:0] Display;
output reg [3:0] Result;
output reg OF;

reg [3:0] Result_reg;

// Wires
wire [3:0] A;
wire [3:0] B;
wire [1:0] S;

always @(A,B,S) begin
    if (S == 1)
        {OF,Result} = A + B;
    else if (S == 0)
        {OF,Result} = A - B;
end 

always @(OF,Result) begin
    case (Result) 
        5'b00000: Display = 7'b1111110;//0
        5'b00001: Display = 7'b0110000;//1
        5'b00010: Display = 7'b1101101;//2
        5'b00011: Display = 7'b1111001;//3
        5'b00100: Display = 7'b0110011;//4
        5'b00101: Display = 7'b1011011;//5
        5'b00110: Display = 7'b1011111;//6
        5'b00111: Display = 7'b1110000;//7
        5'b01000: Display = 7'b1111111;//8
        5'b01001: Display = 7'b1111011;//9
        5'b01010: Display = 7'b1110111;//A
        5'b01011: Display = 7'b0011111;//B
        5'b01100: Display = 7'b1001110;//C
        5'b01101: Display = 7'b0111101;//D
        5'b01110: Display = 7'b1001111;//E
        5'b01111: Display = 7'b1000111;//F
        default: Display = 7'bx;
    endcase

     if (OF == 1)begin
        Result = 4'bx;
        Display = 7'b0011101;
    end

end

endmodule

Answer 1

您在此处推断为闩锁：

always @(A,B,S) begin
    if (S == 1)
        {OF,Result} = A + B;
    else if (S == 0)
        {OF,Result} = A - B;
    // <-- inferred latch because S=2 and S=3 is not described
end

通常不推荐（电平敏感）锁存器。它们具有价值，但您需要小心使用它们，否则您会遇到时间和亚稳定性问题。详情请见

What is inferred latch and how it is created when it is missing else statement in if condition.can anybody explain briefly?
Why does an If statement cause a latch in verilog?

第二个 driver 是因为您在两个 always 街区驾驶 Result。它在模拟器中工作，但合成是非法的。

always @(OF,Result) begin
  // ...

  if (OF == 1)begin
    Result = 4'bx; // <-- second driver on 'Result'. Illegal for synthesis
    Display = 7'b0011101;
  end
end

注意：通常认为将计划合成的东西分配给 X 的值是不好的做法。

要解决多个 driver 错误，您必须在同一个 always 块中对 Result 进行所有分配。移动分配或合并 always 块。

注意：除非需要遵循严格的 1995 编码规范，否则不应在敏感列表中声明信号。而是使用 2001 年添加到 verilog 的 auto-sensitivity 列表（@* 或 @(*)）。你有 2001 支持，因为 1995 不支持逗号作为敏感列表的信号分隔符； 1995 使用 or 作为敏感列表的信号分隔符。

Answer 2

我已经写了同一个问题的答案。您可以签入 link ： Verilog Subtraction and addition

您已推断出 Latch，因为您已取 "S" 的 2 位宽并且您没有为 "S" 的 2 个选项指定 "Result" 的值。

Incomplete if or case statement can potentially be synthesized into a latch. Because for tool, you didn't specify, what to drive on a net for rest of the if/case condition. In this case, tool will try to make a hardware, which will drive the previous values for those conditions. And to do so, a Latch will be inferred.

always @(A,B,S) begin
    if (S == 1)
        {OF,Result} = A + B;
    else if (S == 0)
        {OF,Result} = A - B;
    // What for S == 2 or S == 3?
    // So tool thinks, that you want to have previous value of Result
    // in both cases, and hence it needs to infer a latch for Result to
    // have the previous value.
end

现在，您遇到了多个驱动程序错误，因为 "Result" 正在通过多个 always 块进行驱动。

A "reg" variable, can't have multiple drivers. But a "wire" can certainly have. So, if a net has multiple drivers, then it has to be of "wire" type.

连接到多个驱动程序的信号结果植入

Signal Result Implantation Connected To Multiple Drivers

verilog