VHDL 脚本语法错误
Errors with VHDL Script Syntax
我有这段代码我想做一个 LSFR 但我有几个问题，包括：
ERROR:HDLParsers:3010 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 18. Entity LFSR does not exist.
ERROR:HDLParsers:3312 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 19. Undefined symbol 'std_logic_vector'.
ERROR:HDLParsers:1209 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 19. std_logic_vector: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 20. Undefined symbol 'std_logic'.
ERROR:HDLParsers:1209 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 20. std_logic: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 24. Undefined symbol 's_xor1'.
代码：
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LSFR is port (
clk : in std_logic;
reset,en : in std_logic;
de1,de2 : out std_logic_vector(2 downto 0)
);
end LSFR;
architecture arch of LFSR is
signal etatpresent, etatfutur : std_logic_vector(16 downto 1);
signal s_xor1, s_xor2, s_xor3 : std_logic;
begin
-- Calcul intermediaire des ou exclusifs
s_xor1 <= etatpresent(15) xor etatpresent(1);
s_xor2 <= etatpresent(14) xor etatpresent(1);
s_xor3 <= etatpresent(12) xor etatpresent(1);
-- Calcul de l'état futur en fonction de l'état présent et des ou exclusifs
process(etatpresent) begin
etatfutur(16) <= etatpresent(1);
etatfutur(1) <= etatpresent(2);
etatfutur (2) <= etatpresent(3);
etatfutur (3) <= etatpresent(4);
etatfutur (4) <= etatpresent(5);
etatfutur (5) <= etatpresent(6);
etatfutur (6) <= etatpresent(7);
etatfutur (7) <= etatpresent(8);
etatfutur (8) <= etatpresent(9);
etatfutur (9) <= etatpresent(10);
etatfutur (10) <= etatpresent(11);
etatfutur (11) <= s_xor3;
s_xor3 <= etatpresent(12);
etatfutur (12) <= etatpresent(13);
etatfutur (13) <= s_xor2;
s_xor2 <= etatpresent(14);
etatfutur (14) <= s_xor1;
s_xor1 <= etatpresent(15);
etatfutur (15) <= etatpresent(16);
end process;
process(reset) begin
if (reset = '1' ) then
etatfutur <="0000000000000001";
end if ;
end process;
-- cablage des deux sorties
de1(2 downto 0) <= etatpresent(16 downto 14);
de2 (2 downto 0) <= etatpresent(3 downto 1);
end arch;
您在实体中拼错了 LFSR。 ("LSFR")
虽然您没有识别行号并且它们不匹配，但第一个错误是 LFSR 不是 Martin Zobel 指出的体系结构架构的声明实体。它似乎是实体声明及其结束语句中拼写错误的实体名称。
如果不求助于 Internet 搜索来识别生成错误消息的 VHDL 工具，它似乎不完全符合标准，Maria 可能会在她的评论中找到一些东西，并识别出错误消息的来源。
通常情况下，上下文子句中重复的库名称会被忽略，同一内部声明区域中 use 子句中的重复声明也会被忽略。
整理实体名称和上下文子句（通过删除多余的元素）：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LFSR is -- was LSFR is port (
port (
clk: in std_logic;
reset, en: in std_logic;
de1, de2: out std_logic_vector(2 downto 0)
);
end entity LFSR; -- was end LSFR;
architecture arch of LFSR is -- Line 16, LFSR doesn't match LSFR
signal etatpresent, etatfutur: std_logic_vector(16 downto 1);
signal s_xor1, s_xor2, s_xor3: std_logic;
begin
-- Calcul intermediaire des ou exclusifs
s_xor1 <= etatpresent(15) xor etatpresent(1);
s_xor2 <= etatpresent(14) xor etatpresent(1);
s_xor3 <= etatpresent(12) xor etatpresent(1);
-- Calcul de l'état futur en fonction de l'état présent et des ou exclusifs
process (etatpresent)
begin
etatfutur(16) <= etatpresent(1);
etatfutur(1) <= etatpresent(2);
etatfutur (2) <= etatpresent(3);
etatfutur (3) <= etatpresent(4);
etatfutur (4) <= etatpresent(5);
etatfutur (5) <= etatpresent(6);
etatfutur (6) <= etatpresent(7);
etatfutur (7) <= etatpresent(8);
etatfutur (8) <= etatpresent(9);
etatfutur (9) <= etatpresent(10);
etatfutur (10) <= etatpresent(11);
etatfutur (11) <= s_xor3;
s_xor3 <= etatpresent(12);
etatfutur (12) <= etatpresent(13);
etatfutur (13) <= s_xor2;
s_xor2 <= etatpresent(14);
etatfutur (14) <= s_xor1;
s_xor1 <= etatpresent(15);
etatfutur (15) <= etatpresent(16);
end process;
process (reset, clk) -- added clock to sensitivity list
begin
if reset = '1' then
etatpresent <= "0000000000000001"; -- was etatfutur
elsif rising_edge(clk) and en = '1' then
etatpresent <= etatfutur;
end if;
end process;
-- cablage des deux sorties
de1(2 downto 0) <= etatpresent(16 downto 14);
de2 (2 downto 0) <= etatpresent(3 downto 1);
end architecture arch;
给我们一些分析。请注意，我还将 clk 添加到过程敏感度列表中，更正了重置并添加了 etatpresent 寄存器。
那么有用吗？我们可以通过创建一个小型测试台并模拟来找出答案：
library ieee;
use ieee.std_logic_1164.all;
entity lfsr_tb is
end entity;
architecture fum of lfsr_tb is
signal clk: std_logic := '0';
signal reset: std_logic;
signal en: std_logic;
signal de1: std_logic_vector (2 downto 0);
signal de2: std_logic_vector (2 downto 0);
begin
DUT:
entity work.lfsr
port map (
clk => clk,
reset => reset,
en => en,
de1 => de1,
de2 => de2
);
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if now > 450 ns then
wait;
end if;
end process;
STIMULI:
process
begin
wait for 11 ns;
reset <= '1';
en <= '0';
wait for 20 ns;
reset <= '0';
wait for 20 ns;
en <= '1';
wait for 100 ns;
en <= '0';
wait for 40 ns;
en <= '1';
wait;
end process;
end architecture;
模拟这给了我们一些看起来不太好的东西：
所以发生了什么？
仔细查看 lfsr arch 中未标记的第一个进程显示 s_xor1、s_xor_2 和 s_xor3 有重复的驱动程序，并且其中三个缺少敏感性列表（它们显示在作业的右侧表达式中）。
无需参考您正在实施的 LFSR 算法，我们可以简单地添加缺少的敏感度列表项，并注释掉驱动程序：
-- Calcul de l'état futur en fonction de l'état présent et des ou exclusifs
process (etatpresent, s_xor1, s_xor2, s_xor3)
begin
etatfutur(16) <= etatpresent(1);
etatfutur(1) <= etatpresent(2);
etatfutur (2) <= etatpresent(3);
etatfutur (3) <= etatpresent(4);
etatfutur (4) <= etatpresent(5);
etatfutur (5) <= etatpresent(6);
etatfutur (6) <= etatpresent(7);
etatfutur (7) <= etatpresent(8);
etatfutur (8) <= etatpresent(9);
etatfutur (9) <= etatpresent(10);
etatfutur (10) <= etatpresent(11);
etatfutur (11) <= s_xor3;
-- s_xor3 <= etatpresent(12);
etatfutur (12) <= etatpresent(13);
etatfutur (13) <= s_xor2;
-- s_xor2 <= etatpresent(14);
etatfutur (14) <= s_xor1;
-- s_xor1 <= etatpresent(15);
etatfutur (15) <= etatpresent(16);
end process;
这给了我们一个无误差的波形：
您需要根据算法规范验证 LFSR 操作。
请注意使两个时钟无效是如何工作的。
我有这段代码我想做一个 LSFR 但我有几个问题，包括：
ERROR:HDLParsers:3010 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 18. Entity LFSR does not exist.
ERROR:HDLParsers:3312 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 19. Undefined symbol 'std_logic_vector'.
ERROR:HDLParsers:1209 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 19. std_logic_vector: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 20. Undefined symbol 'std_logic'.
ERROR:HDLParsers:1209 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 20. std_logic: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 24. Undefined symbol 's_xor1'.
代码：
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LSFR is port (
clk : in std_logic;
reset,en : in std_logic;
de1,de2 : out std_logic_vector(2 downto 0)
);
end LSFR;
architecture arch of LFSR is
signal etatpresent, etatfutur : std_logic_vector(16 downto 1);
signal s_xor1, s_xor2, s_xor3 : std_logic;
begin
-- Calcul intermediaire des ou exclusifs
s_xor1 <= etatpresent(15) xor etatpresent(1);
s_xor2 <= etatpresent(14) xor etatpresent(1);
s_xor3 <= etatpresent(12) xor etatpresent(1);
-- Calcul de l'état futur en fonction de l'état présent et des ou exclusifs
process(etatpresent) begin
etatfutur(16) <= etatpresent(1);
etatfutur(1) <= etatpresent(2);
etatfutur (2) <= etatpresent(3);
etatfutur (3) <= etatpresent(4);
etatfutur (4) <= etatpresent(5);
etatfutur (5) <= etatpresent(6);
etatfutur (6) <= etatpresent(7);
etatfutur (7) <= etatpresent(8);
etatfutur (8) <= etatpresent(9);
etatfutur (9) <= etatpresent(10);
etatfutur (10) <= etatpresent(11);
etatfutur (11) <= s_xor3;
s_xor3 <= etatpresent(12);
etatfutur (12) <= etatpresent(13);
etatfutur (13) <= s_xor2;
s_xor2 <= etatpresent(14);
etatfutur (14) <= s_xor1;
s_xor1 <= etatpresent(15);
etatfutur (15) <= etatpresent(16);
end process;
process(reset) begin
if (reset = '1' ) then
etatfutur <="0000000000000001";
end if ;
end process;
-- cablage des deux sorties
de1(2 downto 0) <= etatpresent(16 downto 14);
de2 (2 downto 0) <= etatpresent(3 downto 1);
end arch;
您在实体中拼错了 LFSR。 ("LSFR")
虽然您没有识别行号并且它们不匹配，但第一个错误是 LFSR 不是 Martin Zobel 指出的体系结构架构的声明实体。它似乎是实体声明及其结束语句中拼写错误的实体名称。
如果不求助于 Internet 搜索来识别生成错误消息的 VHDL 工具，它似乎不完全符合标准，Maria 可能会在她的评论中找到一些东西，并识别出错误消息的来源。
通常情况下，上下文子句中重复的库名称会被忽略，同一内部声明区域中 use 子句中的重复声明也会被忽略。
整理实体名称和上下文子句（通过删除多余的元素）：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LFSR is -- was LSFR is port (
port (
clk: in std_logic;
reset, en: in std_logic;
de1, de2: out std_logic_vector(2 downto 0)
);
end entity LFSR; -- was end LSFR;
architecture arch of LFSR is -- Line 16, LFSR doesn't match LSFR
signal etatpresent, etatfutur: std_logic_vector(16 downto 1);
signal s_xor1, s_xor2, s_xor3: std_logic;
begin
-- Calcul intermediaire des ou exclusifs
s_xor1 <= etatpresent(15) xor etatpresent(1);
s_xor2 <= etatpresent(14) xor etatpresent(1);
s_xor3 <= etatpresent(12) xor etatpresent(1);
-- Calcul de l'état futur en fonction de l'état présent et des ou exclusifs
process (etatpresent)
begin
etatfutur(16) <= etatpresent(1);
etatfutur(1) <= etatpresent(2);
etatfutur (2) <= etatpresent(3);
etatfutur (3) <= etatpresent(4);
etatfutur (4) <= etatpresent(5);
etatfutur (5) <= etatpresent(6);
etatfutur (6) <= etatpresent(7);
etatfutur (7) <= etatpresent(8);
etatfutur (8) <= etatpresent(9);
etatfutur (9) <= etatpresent(10);
etatfutur (10) <= etatpresent(11);
etatfutur (11) <= s_xor3;
s_xor3 <= etatpresent(12);
etatfutur (12) <= etatpresent(13);
etatfutur (13) <= s_xor2;
s_xor2 <= etatpresent(14);
etatfutur (14) <= s_xor1;
s_xor1 <= etatpresent(15);
etatfutur (15) <= etatpresent(16);
end process;
process (reset, clk) -- added clock to sensitivity list
begin
if reset = '1' then
etatpresent <= "0000000000000001"; -- was etatfutur
elsif rising_edge(clk) and en = '1' then
etatpresent <= etatfutur;
end if;
end process;
-- cablage des deux sorties
de1(2 downto 0) <= etatpresent(16 downto 14);
de2 (2 downto 0) <= etatpresent(3 downto 1);
end architecture arch;
给我们一些分析。请注意，我还将 clk 添加到过程敏感度列表中，更正了重置并添加了 etatpresent 寄存器。
那么有用吗？我们可以通过创建一个小型测试台并模拟来找出答案：
library ieee;
use ieee.std_logic_1164.all;
entity lfsr_tb is
end entity;
architecture fum of lfsr_tb is
signal clk: std_logic := '0';
signal reset: std_logic;
signal en: std_logic;
signal de1: std_logic_vector (2 downto 0);
signal de2: std_logic_vector (2 downto 0);
begin
DUT:
entity work.lfsr
port map (
clk => clk,
reset => reset,
en => en,
de1 => de1,
de2 => de2
);
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if now > 450 ns then
wait;
end if;
end process;
STIMULI:
process
begin
wait for 11 ns;
reset <= '1';
en <= '0';
wait for 20 ns;
reset <= '0';
wait for 20 ns;
en <= '1';
wait for 100 ns;
en <= '0';
wait for 40 ns;
en <= '1';
wait;
end process;
end architecture;
模拟这给了我们一些看起来不太好的东西：
所以发生了什么？
仔细查看 lfsr arch 中未标记的第一个进程显示 s_xor1、s_xor_2 和 s_xor3 有重复的驱动程序，并且其中三个缺少敏感性列表（它们显示在作业的右侧表达式中）。
无需参考您正在实施的 LFSR 算法，我们可以简单地添加缺少的敏感度列表项，并注释掉驱动程序：
-- Calcul de l'état futur en fonction de l'état présent et des ou exclusifs
process (etatpresent, s_xor1, s_xor2, s_xor3)
begin
etatfutur(16) <= etatpresent(1);
etatfutur(1) <= etatpresent(2);
etatfutur (2) <= etatpresent(3);
etatfutur (3) <= etatpresent(4);
etatfutur (4) <= etatpresent(5);
etatfutur (5) <= etatpresent(6);
etatfutur (6) <= etatpresent(7);
etatfutur (7) <= etatpresent(8);
etatfutur (8) <= etatpresent(9);
etatfutur (9) <= etatpresent(10);
etatfutur (10) <= etatpresent(11);
etatfutur (11) <= s_xor3;
-- s_xor3 <= etatpresent(12);
etatfutur (12) <= etatpresent(13);
etatfutur (13) <= s_xor2;
-- s_xor2 <= etatpresent(14);
etatfutur (14) <= s_xor1;
-- s_xor1 <= etatpresent(15);
etatfutur (15) <= etatpresent(16);
end process;
这给了我们一个无误差的波形：
您需要根据算法规范验证 LFSR 操作。
请注意使两个时钟无效是如何工作的。