右移寄存器-ParallelLoad

Question

我必须创建一个具有并行加载的 n 位移位右移寄存器（此处使用 4 位）。为此，我使用了 a Mux 2 in 1 和 d flip flops。如果 load 是 '1' 则寄存器加载一个值（DataIn)，否则寄存器开始移位。多路复用器的代码是：

entity Mux2in1onebit is
Port ( A : in  STD_LOGIC;
       B : in  STD_LOGIC;
       Q : out  STD_LOGIC;
       sel : in  STD_LOGIC);
end Mux2in1onebit;

architecture Behavioral of Mux2in1onebit is
begin
Q <= A when sel = '0' else
          B;
end Behavioral

触发器代码：

entity FlipFlop is
    Port ( Din : in  STD_LOGIC;
           Q : out  STD_LOGIC;
           Enable : in  STD_LOGIC;
           Clk : in  STD_LOGIC;
           Reset : in  STD_LOGIC);
end FlipFlop;

architecture Behavioral of FlipFlop is
signal Qtemp : std_logic;
begin
    process(clk)  
       begin    
        if(rising_edge(clk)) then
            if(reset = '1') then 
                Qtemp <= '0';
            else
                if (enable = '1') then 
                    Qtemp <= Din;
                else 
                    Qtemp <= Qtemp;
                end if;
            end if;
        end if;
        end process ; 
    Q <= Qtemp;
end Behavioral;

现在在顶层模块中，我已按如下方式连接多路复用器和触发器：

    entity ShiftRegister is
    Port ( DataIn : in  STD_LOGIC_VECTOR (3 downto 0);
           DataOut : out  STD_LOGIC_VECTOR (3 downto 0);
           Enable : in  STD_LOGIC;
              Load :in STD_LOGIC;
              BitIn : in STD_LOGIC;
              Bitout : out STD_LOGIC;
           Reset : in  STD_LOGIC;
           Clk : in  STD_LOGIC);
end ShiftRegister;

architecture Structural of ShiftRegister is

COMPONENT FlipFlop
    PORT(
        Din : IN std_logic;
        Enable : IN std_logic;
        Clk : IN std_logic;
        Reset : IN std_logic;          
        Q : OUT std_logic
        );
    END COMPONENT;
COMPONENT Mux2in1onebit
    PORT(
        A : IN std_logic;
        B : IN std_logic;
        sel : IN std_logic;          
        Q : OUT std_logic
        );
    END COMPONENT;

signal sigdin, sigq : std_logic_vector(3 downto 0);

begin
MBIT3: Mux2in1onebit PORT MAP(
        A => BitIn,
        B => DataIn(3),
        Q => sigdin(3),
        sel => Load
    );
BIT3: FlipFlop PORT MAP(
        Din => sigdin(3),
        Q => sigq(3),
        Enable => Enable,
        Clk => Clk,
        Reset => Reset
    );
MBIT2: Mux2in1onebit PORT MAP(
        A => sigq(3),
        B => DataIn(2),
        Q => sigdin(2),
        sel => Load
    );
BIT2: FlipFlop PORT MAP(
        Din => sigdin(2),
        Q => sigq(2),
        Enable => Enable,
        Clk => Clk,
        Reset => Reset
    );
MBIT1: Mux2in1onebit PORT MAP(
        A => sigq(2),
        B => DataIn(1),
        Q => sigdin(1),
        sel => Load
    );
BIT1: FlipFlop PORT MAP(
        Din => sigdin(1),
        Q => sigq(1),
        Enable => Enable,
        Clk => Clk,
        Reset => Reset
    );
MBIT0: Mux2in1onebit PORT MAP(
        A => sigq(1),
        B => DataIn(0),
        Q => sigdin(0),
        sel => Load
    );
BIT0: FlipFlop PORT MAP(
        Din => sigdin(0),
        Q => sigq(0),
        Enable => Enable,
        Clk => Clk,
        Reset => Reset
    );

BitOut <= sigq(0);
DataOut <= sigdin;

end Structural;

现在，当我模拟上面的代码时，对于 reset = '1'，触发器设置为 0，当 load = '1' 时，DataIn 将按预期加载。但是当 enable = '1' 寄存器不移动时，结果我得到 "0000" 。谢谢。

Answer 1

你的问题不完全是Minimal, Complete, and Verifiable example，缺少刺激和实际结果。

所有三个实体和体系结构对都缺少上下文子句 (library ieee; use ieee.std_logic_1164.all;)，并且 Mux2in1onebit 的体系结构在 end Behavioral 之后缺少一个分号。

修复这些问题后，我编写了一个简单的测试平台：

library ieee;
use ieee.std_logic_1164.all;

entity sr_tb is
end entity;

architecture fum of sr_tb is
    signal datain:     std_logic_vector (3 downto 0) := "1011"; -- load value
    signal dataout:    std_logic_vector (3 downto 0);
    signal enable:     std_logic := '0';
    signal load:       std_logic := '0';
    signal bitin:      std_logic;
    signal bitout:     std_logic;
    signal reset:      std_logic := '0';
    signal clk:        std_logic := '0';
begin
DUT:
    entity work.shiftregister
        port map (
            datain => datain,
            dataout => dataout,
            enable => enable,
            load => load,
            bitin => bitin,
            bitout => bitout,
            reset => reset,
            clk => clk
        );

CLOCK:
    process
    begin
        wait for 5 ns;
        clk <= not clk;
        if now > 160 ns then
            wait;
        end if;
    end process;
STIMULI:
    process
    begin
        wait for 6 ns;
        reset <= '0';
        wait for 10 ns;
        reset <= '1';
        wait for 10 ns;
        reset <= '0';
        wait for 10 ns;
        load <= '1';
        enable <= '1';
        wait for 10 ns;
        load <= '0';
        enable <= '0';
        wait for 10 ns;
        bitin <= '0';
        wait for 10 ns;
        enable <= '1';
        wait for 10 ns;
        bitin <= '1';
        wait for 10 ns;
        bitin <= '0';
        wait for 10 ns;
        wait for 10 ns;
        bitin <= '1';
        wait for 10 ns;
        wait;
    end process;
end architecture;

产生了：

这表明四个触发器的 sigq 输出是正确的，并指出 DataOut 应该从 sigq 而不是 sigdin 分配：

    dataout <= sigdin;  -- should be sigq
end architecture structural;

如果您跟随 sigq(0) 波形，您会看到它的值与刺激一致。

根据您对问题的评论，您还缺少 Enable 在加载时为“1”。

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