使用 reg 输出作为输入 Verilog

Question

所以，我正在研究一个简单的寄存器，它接受同步输入，并且一旦输入被断言，就会保持该状态直到启用复位。

我的代码应该很清楚。这种检查 reg-output 会导致任何问题吗？

    module walk_reg(
        input Walk_Sync,    //pedestrian set walk-request
        input WR_Reset,     //FSM reset, for during the walk service
        input clk,      //clock
        output reg WR   //output
        );


    always @(posedge (clk)) 
    begin
        if(WR_Reset)    //if reset enables, output goes to 0
            WR <= 1'b0;
        else if (WR)    //if WR is already on, keep it on
            WR <= WR;
        else 
            WR <= Walk_Sync;    //if reset is not enabled and WR isn't already one, assign output to Walk_Sync
    end

    endmodule // walk_reg

编辑更改了变量名，忘记在代码中更改了

Answer 1

没有回答，但评论太多了。

always @(posedge (clk)) 
    begin
        if(WR_Reset)    //if reset enables, output goes to 0
            WR <= 1'b0;
        else if (WR)    //if WR is already on, keep it on
            WR <= WR;
        else 
            WR <= Walk_Sync;    //if reset is not enabled and WR isn't already one, assign output to Walk_Sync
    end

等同于：

always @(posedge clk) 
begin
  if (WR_Reset)    //if reset enables, output goes to 0
    WR <= 1'b0;
  else if (!WR)    
    WR <= Walk_Sync;
end

如果不满足任何条件，触发器将保持其值。

duskwuff 的更好建议：

always @(posedge clk) 
begin
  if (WR_Reset)    //if reset enables, output goes to 0
    WR <= 1'b0;
  else if (Walk_Sync)    
    WR <= 1'b1;
end

Answer 2

附带说明一下，WR_Reset 只会在时钟正常工作时重置触发器。在大多数Flop设计中，我们使用ASYNC复位边沿检测然后基于时钟的复位检测。

always @(posedge (clk)) 对比 always @(posedge (clk) or posedge(WR_Reset))

否则用WR做条件赋值没问题。

使用 reg 输出作为输入 Verilog

Using reg output as input Verilog

verilog