Verilog

Question

使用 ModelSim。我正在尝试模拟一个上下两位计数器。它编译正常，但是当我尝试运行模拟时，出现以下错误：

** Error: (vsim-3043) D:/ModelSim/examples/Lab7.v(46): Unresolved reference to 'state'.

模块是：

module TwoBitCounter(input Dir, clock, reset);

reg[1:0] state;

parameter S0 = 2'b00, S1=2'b01, S2=2'b10, S3 = 2'b11;

always @(posedge clock or negedge reset)
    if (reset == 0) state<=S0;

    else case(state)
        S0: if(Dir) state = S1; else state = S3;
        S1: if(Dir) state = S2; else state = S0;
        S2: if(Dir) state = S3; else state = S1;
        S3: if(Dir) state = S0; else state = S2;
    endcase

endmodule

测试台是：

module Counter_TB;

reg Dir, clock, reset;


TwoBitCounter DA0(.Dir(Dir), .clock(clock), .reset(reset) );

initial begin

reset = 0;
Dir = 1;

#5 reset = 1;

forever #205 Dir = ~Dir;

end

initial begin
clock = 0;
forever #25 clock = ~clock;
end



initial #800 $stop;

initial $monitor ("State AB: %b", state);

endmodule

Answer 1

由于state 是TwoBitCounter 模块的内部变量，当您尝试在$monitor 语句中的testbench 模块中直接访问它时会出现错误。您可以使用分层说明符访问它：

initial $monitor(DA0.state);

或者，您可以将 state 声明为 TwoBitCounter 模块的 output 端口并在测试台中连接到它。

Verilog - Error: "Unresolved reference" when simulating

Verilog - Error: "Unresolved reference" when simulating

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