无法解析多个常量

Question

我正在尝试创建 FSM，但出现无法解析多个常量驱动程序的错误

这是我的代码：

 library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    library work;
    use work.all;

    entity fsm is 
        port(
            reset,clk : in std_logic;
            dataout: out std_logic_vector(7 downto 0)
        );
    end entity fsm;

    architecture bhv_fsm of fsm is
    type FSM_TYPE is (standby, ready, encryption, decryption);
    signal pre_state, next_state : FSM_TYPE;
    signal cmd, cancel, busy, acquirekey : std_logic;
    signal controller: std_logic_vector(3 downto 0);
    signal dout: std_logic_vector(7 downto 0);
    begin
    controller <= cmd & cancel & busy & acquirekey;
    P1: process(clk, reset) is

    begin 
        dataout <= "00000000"; 
        if reset='1' then
        next_state <= standby;
        elsif rising_edge(clk) then
            pre_state <= next_state;
        end if;
    end process P1; 

    LC1_LC2: process(pre_state, next_state) is
    variable timer: integer :=0;
    begin
    dataout <= (others => '0');
    next_state <= pre_state;
    case pre_state is
        when standby => 
            if (controller = "0000") then
            next_state <= ready;
            end if;

        when ready =>
            if(timer<10) then
                if (controller = "1000") then
                next_state <= encryption;
                timer:=0;
                controller <= "0010";
                timer:=timer+1;
                elsif (controller = "0000") then
                next_state <= decryption;
                timer:=0;
                controller <= "0010";
                end if;
            timer:=timer+1;
            else
            next_state <= standby;
            end if;

            when encryption =>
                if(controller = "1110") then
                    next_state <= ready;
                elsif(controller = "1011") then
                    dataout <= dout;
                    next_state <= ready;
                end if; 
            -- cmd cancel busy acquire

            when decryption =>
                if(controller = "0110")then
                    next_state <= ready;
                elsif(controller = "0011") then
                    dataout <= dout;
                    next_state <= ready;
                end if; 

    end case;           
    end process LC1_LC2;
    end architecture bhv_fsm;

这些是错误：

Error (10028): Can't resolve multiple constant drivers for net "next_state.standby" at fsm.vhd(33)

Error (10029): Constant driver at fsm.vhd(22)

Error (10028): Can't resolve multiple constant drivers for net "next_state.ready" at fsm.vhd(33)

Error (10028): Can't resolve multiple constant drivers for net "next_state.encryption" at fsm.vhd(33)

Error (10028): Can't resolve multiple constant drivers for net "next_state.decryption" at fsm.vhd(33)

Error (10028): Can't resolve multiple constant drivers for net "controller[3]" at fsm.vhd(21)

Error (10029): Constant driver at fsm.vhd(33)

Error (10028): Can't resolve multiple constant drivers for net "controller[2]" at fsm.vhd(21)

Error (10028): Can't resolve multiple constant drivers for net "controller[1]" at fsm.vhd(21)

Error (10028): Can't resolve multiple constant drivers for net "controller[0]" at fsm.vhd(21)

Answer 1

当您合成 VHDL 时，每个进程都变成硬件块，驱动由该进程驱动的任何信号。如果您从多个进程驱动一个信号，那么您最终会得到多个驱动该信号的硬件块；该信号来自多个地方。换句话说，你短路了。

这通常不是您想要的行为，通常也不是逻辑综合器准备创建的行为。您的代码就是这种情况：

您的代码中有三个并发进程。这个：

controller <= cmd & cancel & busy & acquirekey;

驱动信号controller；这个：

P1: process(clk, reset) is

驱动信号dataout、next_state和pre_state；还有这个：

LC1_LC2: process(pre_state, next_state) is

也驱动信号 controller、next_state 和 data_out。

因此，信号controller、next_state和data_out是由多个进程驱动的；这些信号将由多个硬件驱动。你的合成器不喜欢这个，我很确定这不是你想要的。

你不是在写软件。 VHDL 是一种硬件描述语言。你需要考虑更多的硬件。

不知道你的设计意图；我只能"suspect"。但是，我怀疑你根本不需要这一行：

    dataout <= "00000000";

我怀疑这些行：

    if reset='1' then
    next_state <= standby;

应该是：

    if reset='1' then
    pre_state <= standby;

我怀疑你根本不需要这一行：

 controller <= cmd & cancel & busy & acquirekey;

无法解析多个常量

Can't resolve multiple constant

vhdl