VHDL simulation error: "delta count overflow"

VHDL simulation error: "delta count overflow"

run 50 ns
#KERNEL: stopped at delta: 5000 at time 10 ns.
#KERNEL: Error: KERNEL_0160 Delta count overflow. Increase the iteration limit using -i argument for asim or the matching entry in simulation preferences.
#Error: Fatal error occurred during simulation.

我哪里错了?

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity funct is
    port(x: in std_logic_vector (2 downto 1);
    y: out std_logic);
end funct;

architecture funct of funct is
    signal r, s, q : std_logic_vector(2 downto 0) := "000";
begin
    process
    begin
        wait on x, q;
        r(2) <= not(q(0)) or (not(q(1)) and x(2) and not(x(1)));
        r(1) <= q(2) and not(x(2));
        r(0) <= not(q(1)) and q(0) and x(1);
        s(2) <= q(1) and x(2);
        s(1) <= not(q(2)) and q(0) and not(x(2));
        s(0) <= not(q(2)) and not(q(1)) and not(q(0)) and x(2);
    end process; 

    y <= q(2) and not(q(1)) and q(0);

    process
    begin
        wait on r, s;
        q(0) <= s(0) or (not(r(0)) and q(0)); 
        q(1) <= s(1) or (not(r(1)) and q(1));   
        q(2) <= s(2) or (not(r(2)) and q(2));
    end process;
end funct;

两个进程循环触发:

  • x初始变化时,触发第一个进程,
  • rs是由第一个进程生成的,
  • 这些用于wait第二个过程,
  • 然后生成 q
  • 第一个进程wait中用的是什么

因此,第一个、第二个、第一个...进程的执行会继续执行,但不会增加时间,但会增加增量计数器,直到达到增量计数器限制,然后您会看到您看到的错误。

为了解决这个问题,您需要更正组合逻辑以避免内部循环。

此外,等待信号的过程类似于:

process is
begin
  ... 
  wait on {signals};
end process;

通常写成:

process ({signals}) is
begin
  ...
end process;

如果在流程中写纯组合逻辑,那么其实可以跳过制作流程,所以你的代码可以这样写:

r(2) <= not(q(0)) or (not(q(1)) and x(2) and not(x(1)));
r(1) <= q(2) and not(x(2));
r(0) <= not(q(1)) and q(0) and x(1);
s(2) <= q(1) and x(2);
s(1) <= not(q(2)) and q(0) and not(x(2));
s(0) <= not(q(2)) and not(q(1)) and not(q(0)) and x(2);

y <= q(2) and not(q(1)) and q(0);

q(0) <= s(0) or (not(r(0)) and q(0)); 
q(1) <= s(1) or (not(r(1)) and q(1));   
q(2) <= s(2) or (not(r(2)) and q(2));

并以这种方式编写代码,清楚地揭示了从 q(0)r(0) 再到 q(0).

的组合循环