关键字已存在的 vhdl 错误代码 10500

Question

此代码用于 PRBS（伪随机二进制序列）接收器。它应该采用三个值并模拟 PRBS 生成器，并使用生成的值检查获得的值。但是代码显示已经存在的关键字错误，例如 begin

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee. std_logic_arith.all;
    use ieee. std_logic_unsigned.all;

    entity receiver is
    port(
        inp : in std_logic;
        clock : in std_logic;
        count : out std_logic_vector(4 downto 0);
        check : out std_logic);
    end receiver;

    architecture rec of receiver is
    signal P : std_logic_vector(2 downto 0);
    signal O : std_logic_vector(2 downto 0);

    process (clock)
        variable cnt  : integer range 0 to 3;
        begin
            if clock'event and clock='1'  then
                P <= inp & P(2 downto 1);
                cnt<=cnt+1;
            end if;
            if (cnt = 3) then
                O<=P;
                elseif (cnt >3)
                O <= inp & O(2 downto 1);
            end if;
            if((O(2) xor O(0)) = P(0))  
                check <= '0';
            else
                check <= '1';
                count <= count +1;
            end if;
        end process;
    end rec;

Error (10500): VHDL syntax error at receiver.vhd(18) near text "process"; expecting "begin", or a declaration statement

Error (10500): VHDL syntax error at receiver.vhd(21) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at receiver.vhd(21) near text "and"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at receiver.vhd(24) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"

Error (10500): VHDL syntax error at receiver.vhd(25) near text "then"; expecting "<="

Error (10500): VHDL syntax error at receiver.vhd(28) near text "O"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at receiver.vhd(29) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"

Error (10500): VHDL syntax error at receiver.vhd(31) near text "check"; expecting "<="

Error (10500): VHDL syntax error at receiver.vhd(32) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at receiver.vhd(35) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"

Answer 1

您的实体结构需要如下所示：

entity receiver is
  port (
    -- Your ports
  );
end receiver;

architecture rec of receiver is
  -- Declarations here
begin  -- ** Your code is missing this part

  process (clock)
  begin
    -- your process
  end process;

end rec;

如评论中所述，始终以您看到的第一个错误开始；首先理解并解决那个问题，之后的许多错误通常都会因此消失。

您已将 cnt 声明为变量，然后尝试使用 cnt <= cnt + 1; 递增它，但变量赋值应使用 := 而不是 <=。

下一个错误是您使用 elseif；这不是真正的关键字，看起来您想使用 elsif。此行还缺少 then.

然后您有一行 if((O(2) xor O(0)) = P(0))，它再次缺少 then。

最后，您试图直接增加 count，这是一个 out 端口。这是不可能的，因为您正在尝试读取输出以向其添加一个；有几种方法可以解决这个问题，但我个人会创建一个中间信号（例如 count_s），你在你的过程中使用它，然后将你的输出分配给这个带有 count <= count_s 的信号，位于过程。

解决所有这些问题后，您的代码至少可以编译。

附带说明一下，它可以帮助您更好地垂直对齐代码；您的 end process 应与其开头 process 垂直对齐，依此类推。

关键字已存在的 vhdl 错误代码 10500

vhdl error code 10500 for keywords already present

vhdl