我正在尝试使用 vhdl 制作一个 8 位 4-1 选择器电路。有人能帮我看看这段代码有什么问题吗？

Question

这是vhdl代码。这个没有错误

library IEEE;
use IEEE.std_logic_1164.all;

entity sel4_1 is
   port( A, B, C, D : in std_logic;
     SEL        : in std_logic_vector(1 downto 0);
     outsgnl    : out std_logic );
   end sel4_1;

architecture EX1 of sel4_1 is
begin

process(A, B, C, D, SEL)
begin
case SEL is
   when "00" => outsgnl <= A;
   when "01" => outsgnl <= B;
   when "10" => outsgnl <= C;
   when others => outsgnl <= D;
end case;
end process;

end EX1;

这是有错误的测试平台

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity TESTBENCH is
end TESTBENCH;

architecture RTL of TESTBENCH is

component sel4_1

   port(A,B,C,D : in std_logic_vector(7 downto 0);
        outsgnl : out std_logic);

end component;

signal INA, INB, INC, IND, OUTSGNL : std_logic_vector(7 downto 0);
signal SEL : std_logic_vector(1 downto 0);

begin
   U0: sel4_1 port map(INA, INB, INC, IND, SEL, OUTSGNL);
   process
   begin
     INA <= "11111111";
     INB <= "11110000";
     INC <= "00001111";
     IND <= "00000000";

     SEL <= "00"; wait for 10 ns;
     SEL <= "01"; wait for 10 ns;
     SEL <= "10"; wait for 10 ns;
     SEL <= "11"; wait for 10 ns;

     wait;
   end process;
end RTL;

出现的错误是 testbench.vhdl:19:27: 无法将 'ina' 与信号接口 "ina"

相关联

testbench.vhdl:19:27:（'ina' 的类型是 std_logic）

testbench.vhdl:11:9:（信号接口类型"ina"是std_logic_vector的子类型）

Answer 1

问题是您的实体 sel4_1 和您的组件 sel_4_1 不一样。您的 A、B、C、D 端口在第一个中是 std_logic，但在第二个中是 std_logic_vector(7 downto 0)。

根据您的实际需要更改实体（或组件），它应该可以正常工作。

Answer 2

这是修改后的代码：

library IEEE;
use IEEE.std_logic_1164.all;

entity sel4_1 is
   port( A, B, C, D : in std_logic_vector(7 downto 0);
        SEL         : in std_logic_vector(1 downto 0);
        outsgnl     : out std_logic_vector(7 downto 0) );
   end sel4_1;

architecture EX1 of sel4_1 is
begin

process(A, B, C, D, SEL)
begin
case SEL is
   when "00" => outsgnl <= A;
   when "01" => outsgnl <= B;
   when "10" => outsgnl <= C;
   when others => outsgnl <= D;
end case;
end process;

end EX1;

测试平台：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity TESTBENCH is
end TESTBENCH;

architecture RTL of TESTBENCH is

component sel4_1
   port(A,B,C,D : in std_logic_vector(7 downto 0);
        SEL     : in std_logic_vector(1 downto 0);
        OUTSGNL : out std_logic_vector(7 downto 0));
end component;

signal INA, INB, INC, IND, OUTSGNL : std_logic_vector(7 downto 0);
signal SEL : std_logic_vector(1 downto 0);

begin
   U0: sel4_1 port map(INA, INB, INC, IND, SEL, OUTSGNL);
   process
   begin
     INA <= "11111111";
     INB <= "11110000";
     INC <= "00001111";
     IND <= "00000000";

     SEL <= "00"; wait for 10 ns;
     SEL <= "01"; wait for 10 ns;
     SEL <= "10"; wait for 10 ns;
     SEL <= "11"; wait for 10 ns;

     wait;
   end process;
end RTL;

Answer 3

作为 Hakim（完全正确）建议的替代方案，有一种并发方式可以做同样的事情。

library IEEE;
use IEEE.std_logic_1164.all;

entity sel4_1 is
   port( A, B, C, D : in std_logic_vector(7 downto 0);
        SEL         : in std_logic_vector(1 downto 0);
        outsgnl     : out std_logic_vector(7 downto 0) );
   end sel4_1;

architecture EX1 of sel4_1 is
begin

  with SEL select
    outsgnl <= A when "00",
               B when "01",
               C when "10",
               D when others;
end EX1;

除了时钟进程之外，我宁愿避免进程。灵敏度列表中缺少信号将导致 simulation/synthesis 不匹配。维护这些敏感列表可能会变得很麻烦。如果需要组合过程，列表应该非常小。（而且，是的，有 VHDL-2008 的 all，这很有帮助。）

我正在尝试使用 vhdl 制作一个 8 位 4-1 选择器电路。有人能帮我看看这段代码有什么问题吗？

I'm trying to make a 8bit 4-1 selector circuit using vhdl. can someone help me what's wrong with this code?

vhdl