我收到一条错误消息 1) unexpected genvar 2) undefined i

Question

module clock
  (
 input logic wclk,rclk
 );
  initial begin
    wclk = 1'b0;
    rclk = 1'b0;
  end



task genclock;
begin
  genvar i;
    generate
      begin
    for(i=0;i<20;i++)
    begin
    #10
    wclk=~wclk;
    rclk=~rclk;
    #20
    rclk=~rclk;
    #20
    wclk=~wclk;
    #40
    wclk=~wclk;
    #40
    rclk=~rclk;
    #80
    wclk=~wclk;
    #100
    rclk=~rclk;
    #10
    wclk=~wclk;
    #2
    rclk=~rclk;
    #150
    wclk=~wclk;
    rclk=~rclk;
    #30
    wclk=~wclk;
    #44
    rclk=~rclk;
    end
    #100
    $finish;
    end
    endgenerate
    end
   endtask
   endmodule

Answer 1

Generate一般用于生成modules、functions、tasks等的多个实例，用于重复顶层结构。

genvar 通常用于 generate 块。对于你的情况，你真的不需要 genvar 和 generate.

为您做的小修改示例：

module clock(wclk, rclk);

input reg wclk;
input reg rclk;

initial begin
  wclk = 1'b0;
  rclk = 1'b0;
  $finish;
end

task genclock;
    integer i;

    begin
    for(i=0;i<20;i=i+1) 
      #10
        wclk <= ~wclk;
        rclk <= ~rclk;
        #20
        rclk <= ~rclk;
        #20
        wclk <= ~wclk;
        #40
        wclk <= ~wclk;
        #40
        rclk <= ~rclk;
        #80
        wclk <= ~wclk;
        #100
        rclk <= ~rclk;
        #10
        wclk <= ~wclk;
        #2
        rclk <= ~rclk;
        #150
        wclk <= ~wclk;
        rclk <= ~rclk;
        #30
        wclk <= ~wclk;
        #44
        rclk <= ~rclk;
        #100;

    end

endtask
endmodule

我收到一条错误消息 1) unexpected genvar 2) undefined i

I get a error saying 1) unexpected genvar 2) undefined i

verilog

system-verilog