递归自实例化组件[VHDL]

Question

我正在用 VHDL 开始一个大项目，我希望编写每个基本组件（加法器、多路复用器、寄存器...），使它们尽可能有序。

我正在考虑为每个实体使用不同的架构（通过不同的抽象层或不同类型的实现），然后 select 使用配置。

我的问题是：是否可以递归地自实例化组件但使用不同的配置？

例如，让我们以加法器为例：

entity ADDER is 
  generic( ... );
  port( ... );
end entity ADDER;

那么我想要不同类型的架构，例如：

-- Behavioral Add
architecture BHV of ADDER is
  out <= A + B;
end architecture BHV;


-- Ripple Carry Adder
architecture RCA of ADDER is 
  ...
end architecture RCA;


-- Carry Select Adder
architecture CSA of ADDER is
  component ADDER --   <== this should be configured as RCA
  ...
end architecture CSA;

是否可以将进位 Select 内部使用的加法器配置为波纹进位，而不会在无限实例化循环中结束？

Answer 1

是的，可以使用 Ripple Carry 配置进位 Select 内部使用的加法器，而不会在无限实例化循环中结束。对于递归实例化，需要一个 终止条件 - 终止递归的条件。配置正在执行该角色。

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity ADDER is 
  generic( WIDTH : positive := 8 );
  port( CIN  : in  std_logic;
        A    : in  std_logic_vector(WIDTH-1 downto 0);
        B    : in  std_logic_vector(WIDTH-1 downto 0);
        F    : out std_logic_vector(WIDTH-1 downto 0);
        COUT : out std_logic);
end entity ADDER;

-- Ripple Carry Adder
architecture RCA of ADDER is 
  signal CIN0 : unsigned(0 downto 0);
  signal FIN  : unsigned(WIDTH downto 0);
begin
  CIN0(0) <= CIN;
  FIN <= resize(unsigned(A), WIDTH+1) + resize(unsigned(B), WIDTH+1) + CIN0; -- yes, I know it's not a ripple carry adder
  F    <= std_logic_vector(FIN(WIDTH-1 downto 0));
  COUT <= FIN(WIDTH);
end architecture RCA;

-- Carry Select Adder
architecture CSA of ADDER is
  component ADDER is 
    generic( WIDTH : positive );
    port( CIN  : in  std_logic;
          A    : in  std_logic_vector(WIDTH-1 downto 0);
          B    : in  std_logic_vector(WIDTH-1 downto 0);
          F    : out std_logic_vector(WIDTH-1 downto 0);
          COUT : out std_logic);
  end component ADDER;
  signal F0, F1       : std_logic_vector(WIDTH-1 downto 0);
  signal COUT0, COUT1 : std_logic;
begin
  ADD0: ADDER generic map( WIDTH => WIDTH)
    port map ( 
          CIN  => '0'  ,
          A    => A    ,
          B    => B    ,
          F    => F0    ,
          COUT => COUT0 );
  ADD1: ADDER generic map( WIDTH => WIDTH)
    port map ( 
          CIN  => '1'  ,
          A    => A    ,
          B    => B    ,
          F    => F1    ,
          COUT => COUT1 );
  COUT <= COUT1 when CIN = '1' else COUT0;
  F    <= F1    when CIN = '1' else F0;
end architecture CSA;

-- here's the configuration
configuration CSAC of ADDER is
  for CSA
    for all: ADDER
      use entity work.ADDER(RCA);
    end for;
  end for;
end configuration CSAC;

http://www.edaplayground.com/x/2Yu3

递归自实例化组件[VHDL]

Recursive self-instantiation component [VHDL]

architecture

recursion

configuration

entity

vhdl