为什么在 VHDL 中尝试初始化此记录时出现 "invalid aggregate" 错误？

Question

我想初始化一条记录。我在网上查看并遵循 this answer 的风格，但我收到以下错误：

来自 Aldec Linter：

Compile Architecture "TB_ARCHITECTURE" of Entity "ten_gig_filter_tb" Error: COMP96_0079: mgmt_regs_rx_TB.vhd : (97, 65): Invalid aggregate. Error: COMP96_0077: mgmt_regs_rx_TB.vhd : (97, 65): Undefined type of expression. Expected type 'tAPB_IBUS_RECORD'.

来自 XVHDL Linter：

type of aggregate cannot be determined without context; 0 visible types match here, 32 matches.

这是我的代码：

-- APB BUS - CPU interface
type tAPB_IBUS_RECORD is record

    pclk        : std_logic;                --APB Clock, all transactions are synced to this clock
    presetn     : std_logic;                --APB active low reset.
    pprot       : std_logic_vector(2 downto 0); --APB protection encoding.
    pselx       : std_logic;            --slave select pin, when asserted, will activate the slave
    penable     : std_logic;            -- Enable pin is asserted by the master after the first clock cycle and consecutively until the 
                                        -- the end of transcation indicated by pready = '1'
    pwrite      : std_logic;            -- APB Write/Read signal - '1' Write with pselx= '1', '0' - Read along with pselx = '1'
    pstrb       : std_logic_vector(3 downto 0); -- Write strobe to enable sparse data transfer on the write bus, 0 - byte lane on pwdata(7-0)
    paddr       : std_logic_vector(19 downto 0); -- 20 bit address bus
    pwdata      : std_logic_vector(31 downto 0); -- 32 bit data bus 
end record;

signal iAPB_BUS_IN         : tAPB_IBUS_RECORD := (
                             pclk => '0', presetn => '0', pprot => (others => '1'),
                             pselx => '1', pwrite => (others => '0'), penable => '1',
                             pstrb => (others => '1'), paddr => (others => '0'),
                             pwdata => (others => '0')
                           );

Answer 1

因为这个位错了:

pwrite => (others => '0'),

应该是

pwrite => '0',

因为 pwrite 的类型是 std_logic.

http://www.edaplayground.com/x/5eay

为什么在 VHDL 中尝试初始化此记录时出现 "invalid aggregate" 错误？

Why am I getting an "invalid aggregate" error when trying to initialize this record in VHDL?

initialization

record

vhdl