verilog 期望在生成块附近出现分号错误

Question

多年来我一直在使用 verilog，但最近我正在用 verilog 测试一些东西。在 ncvlog 编译期间，我有一个错误，我找不到原因。下面是代码（尚未完成）。

`include "default.v"

module conv (
    input clr,
    input clk,
    input start_conv,
    output integer raddr,
    output integer waddr,
    input  real data_in,
    output real data_out
);

parameter NUM_CONV = `DEF_NUM_CONV;


genvar i;
generate
for (i=0; i<NUM_CONV; i=i+1) begin : uconv
unit_conv inst() (
    .clr (clr),
    .clk (clk),
    .start (start_conv),
    .rreq (rreq[i]),
    .raddr (raddr[i]),
    .rdata (rdata[i]),
    .wreq (wreq[i]),
    .waddr (waddr[i]),
    .wdata (wdata[i])
);

end
endgenerate

endmodule

我得到的错误如下：

ckim@stph45:~/Neuro/convhw] ncvlog -sv conv.v
ncvlog: 12.20-s008: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
unit_conv inst() (
                 |
ncvlog: *E,EXPSMC (conv.v,19|17): expecting a semicolon (';') [12.1.2][7.1(IEEE)].

生成实例的端口映射语法有误吗？根据这似乎是正确的......顺便说一句，我用 ncvlog -SV conv.v.

编译

Answer 1

考虑以下因素：

unit_conv inst (
    .clr (clr),
    .clk (clk),
    .start (start_conv),
    .rreq (rreq[i]),
    .raddr (raddr[i]),
    .rdata (rdata[i]),
    .wreq (wreq[i]),
    .waddr (waddr[i]),
    .wdata (wdata[i])
);

verilog 期望在生成块附近出现分号错误

verilog expecting a semicolon error near generate block

verilog

system-verilog