VHDL 允许在条件语句中从无符号到 std_logic_vector 的转换
VHDL permissive conversion from unsigned to std_logic_vector in conditional statement
我想知道为什么在条件语句中执行从无符号到 std_logic_vector 的错误转换时我没有收到警告/错误
--Naturally wrong when input length is not 4, will always be false
if input = std_logic_vector(to_unsigned(pattern_int,4)) then
而它是在通常的其他向量伪装中检测到的。
-- for this you will get a warning, e.g vector truncated
temp <= std_logic_vector(to_unsigned(pattern_int,4));
具有工作语法的简化代码 (MVCE) 如下所示：
Link to EDA PlayGround（包含 "dut" 的代码及其测试平台）
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity vector_test is
port ( CLOCK : in std_logic;
RESET : in std_logic;
INPUT : in std_logic_vector(7 downto 0);
OUTPUT : out std_logic);
end entity;
architecture rtl of vector_test is
constant pattern_int : integer := 16#80#;
--signal temp : std_logic_vector(7 downto 0);
begin
process(CLOCK,RESET,INPUT)
begin
-- for this you will get a warning, e.g vector truncated
--temp <= std_logic_vector(to_unsigned(pattern_int,4));
if RESET = '1' then
output <= '0';
elsif rising_edge(CLOCK) then
--Naturally wrong, output will alway be 0
--if input = std_logic_vector(to_unsigned(pattern_int,4)) then
if input = std_logic_vector(to_unsigned(pattern_int,input'length)) then
output <= '1';
else
output <= '0';
end if;
end if;
end process;
end architecture;
测试平台使问题真正完整（它已经在 EDA Playground 上可用，但不幸的是你必须注册才能玩...）
library IEEE;
use IEEE.std_logic_1164.all;
entity test is
end entity;
architecture beh of test is
signal comparison_output : std_logic;
signal input_stim : std_logic_vector(7 downto 0) := x"33";
signal clock : std_logic := '0';
signal reset : std_logic := '1';
begin
vt: entity work.vector_test
port map ( CLOCK => clock,
RESET => reset,
input => input_stim,
output => comparison_output );
clocking: process(clock)
begin
clock <= not clock after 16.7 ns;
end process;
stimuli: process
begin
reset <= '0' after 20 ns;
input_stim <= x"36" after 100 ns;
input_stim <= x"80" after 100 ns;
wait;
end process;
end architecture;
我想知道为什么在条件语句
中执行从无符号到 std_logic_vector 的错误转换时我没有收到警告/错误
IEEE Std 1076-2008 9.2.3 关系运算符第 3 和 4 段：
The equality and inequality operators (= and /=) are defined for all types other than file types and protected types. The equality operator returns the value TRUE if the two operands are equal and returns the value FALSE otherwise. The inequality operator returns the value FALSE if the two operands are equal and returns the value TRUE otherwise.
Two scalar values of the same type are equal if and only if the values are the same. Two composite values of the same type are equal if and only if for each element of the left operand there is a matching element of the right operand and vice versa, and the values of matching elements are equal, as given by the predefined equality operator for the element type. In particular, two null arrays of the same type are always equal. Two values of an access type are equal if and only if they both designate the same object or they both are equal to the null value for the access type.
如果两个 std_logic_vector 值的长度不匹配，相等性测试将 return FALSE。一个port中声明的INPUT的长度为8，unsigned转换为std_logic_vector的长度为4（来自[=56=的第二个参数），自然指定[=的长度59=]ed 未签名）。
如果您取消对 temp 和 运行 代码的注释，您将在模拟期间收到错误消息。
14.7.3.4 信号更新第 1 段和第 2 段：
For a scalar signal S, both the driving and effective values shall belong to the subtype of the signal. For a composite signal R, an implicit subtype conversion is performed to the subtype of R; for each element of R, there shall be a matching element in both the driving and the effective value, and vice versa.
In order to update a signal during a given simulation cycle, the kernel process first determines the driving and effective values of that signal. The kernel process then updates the variable containing the driving value with the newly determined driving value. The kernel also updates the variable containing the current value of the signal with the newly determined effective value, as follows:
a) If S is a scalar signal, the effective value of S is used to update the current value of S. A check is made that the effective value of S belongs to the subtype of S. An error occurs if this subtype check fails. Finally, the effective value of S is assigned to the variable representing the current value of the signal.
b) If S is a composite signal (including a slice of an array), the effective value of S is implicitly converted to the subtype of S. The subtype conversion checks that for each element of S there is a matching element in the effective value and vice versa. An error occurs if this check fails. The result of this subtype conversion is then assigned to the variable representing the current value of S.
条件的评估未定义为错误，而更新信号要求右侧的表达式中有匹配元素，但失败了。
将关系相等的数组值与空数组进行比较并得到 FALSE return 值是完全有效的。
第19行报如下错误是temp assignment uncommented:
ghdl -a vector_test.vhdl
ghdl -e vector_test
ghdl -r vector_test
../../src/ieee/numeric_std-body.v93:2151:7:@0ms:(assertion warning): NUMERIC_STD.TO_UNSIGNED: vector truncated
./vector_test:error: bound check failure at vector_test.vhdl:19
./vector_test:error: simulation failed
除了 14.7.3.4（12.6.2 信号值的传播，-1993 中的第 12 段）规定的绑定检查失败错误之外，我们还看到来自包 numeric_std 函数 to_unsigned 的警告报告除零以外的除法余数：
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable I_VAL : NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL = 0) then
assert NO_WARNING
report "NUMERIC_STD.TO_UNSIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_UNSIGNED;
这是由于提供的 SIZE 参数 (4) 不足以包含常量 pattern_int 的自然值，值 16#80# 转换为需要 8 位 SIZE 的二进制。
能够使用顶级端口执行 vector_test 取决于实现。
14.2 设计实体的详细说明第 7 段：
An implementation may allow, but is not required to allow, a design entity at the root of a design hierarchy to have generics and ports. If an implementation allows these top-level interface objects, it may restrict their allowed forms (that is, whether they are allowed to be interface types, subprograms, packages, or objects), and, in the case of interface objects, their allowed types and modes in an implementation-defined manner.
简单地说，对于某些模拟器，您的代码是 MCVE，而对于其他模拟器则不是。您的测试平台可以包含在您的问题中。我们看到的错误 运行ning ghdl 发生在 if 语句之外，条件是评估 CLOCK.
的上升沿
我想知道为什么在条件语句中执行从无符号到 std_logic_vector 的错误转换时我没有收到警告/错误
--Naturally wrong when input length is not 4, will always be false
if input = std_logic_vector(to_unsigned(pattern_int,4)) then
而它是在通常的其他向量伪装中检测到的。
-- for this you will get a warning, e.g vector truncated
temp <= std_logic_vector(to_unsigned(pattern_int,4));
具有工作语法的简化代码 (MVCE) 如下所示：
Link to EDA PlayGround（包含 "dut" 的代码及其测试平台）
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity vector_test is
port ( CLOCK : in std_logic;
RESET : in std_logic;
INPUT : in std_logic_vector(7 downto 0);
OUTPUT : out std_logic);
end entity;
architecture rtl of vector_test is
constant pattern_int : integer := 16#80#;
--signal temp : std_logic_vector(7 downto 0);
begin
process(CLOCK,RESET,INPUT)
begin
-- for this you will get a warning, e.g vector truncated
--temp <= std_logic_vector(to_unsigned(pattern_int,4));
if RESET = '1' then
output <= '0';
elsif rising_edge(CLOCK) then
--Naturally wrong, output will alway be 0
--if input = std_logic_vector(to_unsigned(pattern_int,4)) then
if input = std_logic_vector(to_unsigned(pattern_int,input'length)) then
output <= '1';
else
output <= '0';
end if;
end if;
end process;
end architecture;
测试平台使问题真正完整（它已经在 EDA Playground 上可用，但不幸的是你必须注册才能玩...）
library IEEE;
use IEEE.std_logic_1164.all;
entity test is
end entity;
architecture beh of test is
signal comparison_output : std_logic;
signal input_stim : std_logic_vector(7 downto 0) := x"33";
signal clock : std_logic := '0';
signal reset : std_logic := '1';
begin
vt: entity work.vector_test
port map ( CLOCK => clock,
RESET => reset,
input => input_stim,
output => comparison_output );
clocking: process(clock)
begin
clock <= not clock after 16.7 ns;
end process;
stimuli: process
begin
reset <= '0' after 20 ns;
input_stim <= x"36" after 100 ns;
input_stim <= x"80" after 100 ns;
wait;
end process;
end architecture;
我想知道为什么在条件语句
中执行从无符号到 std_logic_vector 的错误转换时我没有收到警告/错误IEEE Std 1076-2008 9.2.3 关系运算符第 3 和 4 段：
The equality and inequality operators (= and /=) are defined for all types other than file types and protected types. The equality operator returns the value TRUE if the two operands are equal and returns the value FALSE otherwise. The inequality operator returns the value FALSE if the two operands are equal and returns the value TRUE otherwise.
Two scalar values of the same type are equal if and only if the values are the same. Two composite values of the same type are equal if and only if for each element of the left operand there is a matching element of the right operand and vice versa, and the values of matching elements are equal, as given by the predefined equality operator for the element type. In particular, two null arrays of the same type are always equal. Two values of an access type are equal if and only if they both designate the same object or they both are equal to the null value for the access type.
如果两个 std_logic_vector 值的长度不匹配，相等性测试将 return FALSE。一个port中声明的INPUT的长度为8，unsigned转换为std_logic_vector的长度为4（来自[=56=的第二个参数），自然指定[=的长度59=]ed 未签名）。
如果您取消对 temp 和 运行 代码的注释，您将在模拟期间收到错误消息。
14.7.3.4 信号更新第 1 段和第 2 段：
For a scalar signal S, both the driving and effective values shall belong to the subtype of the signal. For a composite signal R, an implicit subtype conversion is performed to the subtype of R; for each element of R, there shall be a matching element in both the driving and the effective value, and vice versa.
In order to update a signal during a given simulation cycle, the kernel process first determines the driving and effective values of that signal. The kernel process then updates the variable containing the driving value with the newly determined driving value. The kernel also updates the variable containing the current value of the signal with the newly determined effective value, as follows:
a) If S is a scalar signal, the effective value of S is used to update the current value of S. A check is made that the effective value of S belongs to the subtype of S. An error occurs if this subtype check fails. Finally, the effective value of S is assigned to the variable representing the current value of the signal.
b) If S is a composite signal (including a slice of an array), the effective value of S is implicitly converted to the subtype of S. The subtype conversion checks that for each element of S there is a matching element in the effective value and vice versa. An error occurs if this check fails. The result of this subtype conversion is then assigned to the variable representing the current value of S.
条件的评估未定义为错误，而更新信号要求右侧的表达式中有匹配元素，但失败了。
将关系相等的数组值与空数组进行比较并得到 FALSE return 值是完全有效的。
第19行报如下错误是temp assignment uncommented:
ghdl -a vector_test.vhdl
ghdl -e vector_test
ghdl -r vector_test
../../src/ieee/numeric_std-body.v93:2151:7:@0ms:(assertion warning): NUMERIC_STD.TO_UNSIGNED: vector truncated
./vector_test:error: bound check failure at vector_test.vhdl:19
./vector_test:error: simulation failed
除了 14.7.3.4（12.6.2 信号值的传播，-1993 中的第 12 段）规定的绑定检查失败错误之外，我们还看到来自包 numeric_std 函数 to_unsigned 的警告报告除零以外的除法余数：
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable I_VAL : NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL = 0) then
assert NO_WARNING
report "NUMERIC_STD.TO_UNSIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_UNSIGNED;
这是由于提供的 SIZE 参数 (4) 不足以包含常量 pattern_int 的自然值，值 16#80# 转换为需要 8 位 SIZE 的二进制。
能够使用顶级端口执行 vector_test 取决于实现。
14.2 设计实体的详细说明第 7 段：
An implementation may allow, but is not required to allow, a design entity at the root of a design hierarchy to have generics and ports. If an implementation allows these top-level interface objects, it may restrict their allowed forms (that is, whether they are allowed to be interface types, subprograms, packages, or objects), and, in the case of interface objects, their allowed types and modes in an implementation-defined manner.
简单地说，对于某些模拟器，您的代码是 MCVE，而对于其他模拟器则不是。您的测试平台可以包含在您的问题中。我们看到的错误 运行ning ghdl 发生在 if 语句之外，条件是评估 CLOCK.