何时计算(系统)Verilog 参数?

When are (System)Verilog parameters calculated?

说我定义 module Foo #(parameter a = 8, parameter b= $clog2(a)) ...

然后实例化

Foo #(.a(16)) bar (...)

默认参数b是什么时候计算的?基于a的实际值还是a的默认值?实例栏看到 b=3 还是 b=4?

始终是最终值。

23.10 覆盖模块参数 1800-2012 LRM 中的部分 描述了编译器设置参数值的详细过程。基本上,编译器可以找出参数值之间的依赖关系,因为它对您可以对参数值进行的允许表达式施加了限制。

23.10.3 Parameter dependence

A parameter (for example, memory_size) can be defined with an expression containing another parameter (for example, word_size). However, overriding a parameter, whether by a defparam statement or in a module instantiation statement, effectively replaces the parameter definition with the new expression. Because memory_size depends on the value of word_size, a modification of word_size changes the value of memory_size. For example, in the following parameter declaration, an update of word_size, whether by defparam statement or in an instantiation statement for the module that defined these parameters, automatically updates memory_size. If memory_size is updated due to either a defparam or an instantiation statement, then it will take on that value, regardless of the value of word_size. parameter word_size = 32, memory_size = word_size * 4096;