(vhdl) std_logic_vector 值

Question

我有一个包含以下 3 个文件的项目，我在 CA 文件中遇到此错误：

第 65 行：state_int 附近的类型错误；当前类型std_logic_vector；预期类型 std_logic
ERROR:HDLCompiler:854 - "" 第 40 行：由于先前的错误而忽略了单元。

CA 文件

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CA is

    port(clk,rst:in std_logic;
             state:out std_logic_vector(0 to 8)
            );

end CA;

architecture Behavioral of CA is

    Component cell
        port(L,R,clk,rst:in std_logic;
                 state:out std_logic
            );
    end component;

    Component cellm
        port(L,R,clk,rst:in std_logic;
                 state:out std_logic
            );
    end component;

    signal state_int:std_logic_vector(0 to 8);

begin


    state <= state_int; 
    U_cell0:cell

    port map(clk => clk,
                rst =>rst,
                L => '0',
                R => state_int,
                state => state_int(0)
                );


end Behavioral;

细胞文件

entity cell is

    port(L,R,clk,rst:in std_logic;
                 state:out std_logic
            );

end cell;

architecture Behavioral of cell is

signal state_pr,state_nx:std_logic;

begin

    state_nx <= ((not L) and R and state_pr) or (L and (not R));

    Process(clk,rst)
    Begin
        if rst = '0' then
            state_pr <= '0';    
        elsif rising_edge(clk) then
            state_pr <= state_nx;
        end if;
    end process;    

end Behavioral;

CELLM 文件

entity cellm is

    port(L,R,clk,rst:in std_logic;
                 state:out std_logic
            );

end cellm;

architecture Behavioral of cellm is

    signal state_pr,state_nx:std_logic;

begin

    state_nx <= ((not L) and R and state_pr) or (L and (not R));

    Process(clk,rst)
    Begin
        if rst = '0' then
            state_pr <= '1';    
        elsif rising_edge(clk) then
            state_pr <= state_nx;
        end if;
    end process;
end Behavioral;

我做错了什么？

Answer 1

其实你的设计存在三个问题。评论中提到了前两个问题：

您正在尝试连接一个 std_logic_vector 信号 state_int 和一个 std_logic 端口 R.显然，由于不匹配（单车道与多车道），这将不起作用
在下一行中，您还尝试连接一个 std_logic_vector 信号 state 和一个 std_logic 端口 state_int(0).
你的细胞实体还有另一个问题。 state 输出从未分配给任何东西。所以单元格实体不会有实际输出。您最终可能会收到编译器关于此的警告。

(vhdl) std_logic_vector 值

(vhdl) std_logic_vector value

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