VHDL 数组 - 我如何声明一个未知大小的数组并使用它
VHDL arrays - How do i declare an array of unknown size and use it
我的要求是从输入文件中读取数据位并将数据写入 vhdl 中的内存阵列（输出）。
由于我不知道输入文件中的数据量，我需要声明未知大小的数组并在后期将数据分配给内存。
我的代码如下：
声明：
PACKAGE io IS
type memory is array (natural range<>) of std_logic_vector(3 downto 0);
END;
entity File_io is
port (
clk: in std_logic;
Data_memory: out memory
);
end entity;
architecture behav of File_io is
signal mem: memory;
begin
process(clk)
begin
for i in 0 to 15 loop -- Took just 16 values for explaination purpose.
-- i may need more values to be written which is unknown.
mem(i) <= std_logic_vector(to_unsigned(i, 4));
end loop;
Data_memory <= mem;
end process;
end architecture behav;
我已将实际代码最小化到我的确切要求。忽略任何语法错误。
问题是我无法为不受约束的数组赋值，即未定义大小。
我该怎么做呢 ？有什么建议或替代方案吗？指导我
读取文件两次，第一次确定行数。例如
编辑： 终于可以使用 vhdl 模拟器了。修复了代码。
我最近一直在 VHDL、C++、C#、matlab 和 python 之间切换，以至于我一直在混合语法。
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
entity file_io is
generic (
data_width : positive := 4;
file_name : string
);
port (
clk : in std_logic;
file_output : out std_logic_vector(data_width-1 downto 0) := (others => '0')
);
end entity file_io;
architecture behaviour of file_io is
impure function get_line_count return positive is
file file_pointer : text;
variable line_data : line;
variable lineCount : natural := 0;
begin
file_open(file_pointer, file_name, read_mode);
while not endfile(file_pointer) loop
readline(file_pointer, line_data);
lineCount := lineCount + 1;
end loop;
file_close(file_pointer);
return lineCount;
end function get_line_count;
constant memory_size : positive := get_line_count;
subtype data_type is std_logic_vector(data_width-1 downto 0);
type memory_type is array (0 to memory_size-1) of data_type;
impure function get_data return memory_type is
file file_pointer : text;
variable line_data : line;
variable line_value : bit_vector(data_width-1 downto 0);
variable memory : memory_type;
variable index : natural := 0;
begin
file_open(file_pointer, file_name, read_mode);
while not endfile(file_pointer) loop
readline(file_pointer, line_data);
read(line_data, line_value);
memory(index) := to_stdlogicvector(line_value);
index := index + 1;
end loop;
file_close(file_pointer);
return memory;
end function get_data;
constant memory : memory_type := get_data;
signal index : natural := 0;
begin
process(clk)
begin
if rising_edge(clk) then
file_output <= memory(index);
if (index < memory_size-1) then
index <= index + 1;
else
index <= 0;
end if;
end if;
end process;
end architecture behaviour;
和测试台：
library IEEE;
use IEEE.std_logic_1164.all;
entity file_io_tb is
end entity file_io_tb;
architecture behaviour of file_io_tb is
signal clk : std_logic := '0';
constant data_width : positive := 4;
signal data : std_logic_vector(data_width-1 downto 0);
begin
file_io_inst : entity work.file_io
generic map(
data_width => 4,
file_name => "data_file.txt"
)
port map(
clk => clk,
file_output => data
);
clk_prc : process
begin
loop
clk <= '0', '1' after 1 ns;
wait for 2 ns;
end loop;
end process;
end architecture behaviour;
data_file.txt 刚好包含
0101
1010
1100
0011
...
这对我来说很好...
查看您的其他问题 - 提供了一个示例内存初始化文件以及读取它的问题。
合并该修复并使用方法 J.H。 Bonarius 建议产生 Minimal, Complete and Verifiable example:
library ieee;
use ieee.std_logic_1164.all;
PACKAGE io IS
type memory is array (natural range<>) of std_logic_vector(3 downto 0);
function iswhitespace (inpstr: in string) return boolean;
END;
package body io is
function iswhitespace (inpstr: in string) return boolean is
constant NBSP: character := character'val(128);
begin
for i in inpstr'range loop
if inpstr(i) /= ' ' and inpstr(i) /= NBSP and inpstr(i) /= HT then
exit;
elsif i = inpstr'RIGHT then
return TRUE;
end if;
end loop;
return FALSE;
end function;
end package body;
library ieee;
use ieee.std_logic_1164.all;
use work.io.all;
entity File_io is
generic (
constant MEMORY_SIZE: natural := 42;
constant filename: string := "C:\Users\ChowdaryS\Downloads\topo.bin"
);
port (
clk: in std_logic;
Data_memory: out memory (0 to MEMORY_SIZE - 1)
);
end entity;
architecture foo of File_io is
signal mem: memory (0 to MEMORY_SIZE - 1); -- ADDED subtype indication
use ieee.numeric_std.all; -- MISSING cntext item
use std.textio.all;
signal mem_inited: boolean := FALSE; -- ADDED
begin
process(clk)
file f: text open read_mode is filename;
variable L: line;
variable i: integer:= 0;
variable b: bit_vector(3 downto 0);
begin
if not mem_inited then
i := 0;
while not endfile(f) loop
readline(f, L);
while L.all'length >= b'length and not iswhitespace(L.all) loop
read(L, b);
mem(i) <= to_stdlogicvector(b);
i := i + 1;
end loop;
end loop;
report "mem values loaded = " & integer'image(i);
mem_inited <= TRUE;
end if;
end process;
Data_memory <= mem;
end architecture foo;
有变化。函数 iswhitespace 已添加到包 io 中。您可以看到上面提到的权衡问题以及是否需要。
对输出端口的分配已移出进程。假定您将在该过程中对 mem 进行某种写入。
还有一个测试台实例化 file_io 并确定内存数组的大小，将其作为通用传递。
library ieee;
use ieee.std_logic_1164.all;
use work.io.all;
entity file_io_tb is
end entity;
architecture foo of file_io_tb is
constant MEMSIZ: natural := 16;
constant filename: string := "topo.bin"; -- found locally.
signal clk: std_logic := '0';
signal Data_memory: memory (0 to MEMSIZ - 1);
use std.textio.all;
impure function getarraysize return natural is
variable L: Line;
variable i: natural;
variable b: bit_vector (3 downto 0);
file f: text open read_mode is filename;
begin
i := 0;
while not endfile(f) loop
readline(f, L);
while L.all'length >= b'length and not iswhitespace(L.all) loop
read(L, b);
i := i + 1;
end loop;
end loop;
report " memory size = " & integer'image(i);
return i;
end function;
begin
DUT:
entity work.file_io
generic map (MEMORY_SIZE => getarraysize, filename => filename)
port map (
clk => clk,
Data_memory => Data_memory
);
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if now > 50 ns then
wait;
end if;
end process;
end architecture;
该功能是在细化时执行文件读取以设置通用。
我们看到初始化内存：
使用的 topo.bin 副本在第一行有四个尾随空格：
10101100 11010100 10101100 11010100
11111110 10111001 11111110 10111001
波形中显示的值与来自 topo.bin.
的以上两行匹配
（所有这些都是为了在另一个问题中找到空白问题而写的）。
我的要求是从输入文件中读取数据位并将数据写入 vhdl 中的内存阵列（输出）。 由于我不知道输入文件中的数据量，我需要声明未知大小的数组并在后期将数据分配给内存。
我的代码如下：
声明：
PACKAGE io IS
type memory is array (natural range<>) of std_logic_vector(3 downto 0);
END;
entity File_io is
port (
clk: in std_logic;
Data_memory: out memory
);
end entity;
architecture behav of File_io is
signal mem: memory;
begin
process(clk)
begin
for i in 0 to 15 loop -- Took just 16 values for explaination purpose.
-- i may need more values to be written which is unknown.
mem(i) <= std_logic_vector(to_unsigned(i, 4));
end loop;
Data_memory <= mem;
end process;
end architecture behav;
我已将实际代码最小化到我的确切要求。忽略任何语法错误。
问题是我无法为不受约束的数组赋值，即未定义大小。 我该怎么做呢 ？有什么建议或替代方案吗？指导我
读取文件两次，第一次确定行数。例如
编辑： 终于可以使用 vhdl 模拟器了。修复了代码。 我最近一直在 VHDL、C++、C#、matlab 和 python 之间切换，以至于我一直在混合语法。
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
entity file_io is
generic (
data_width : positive := 4;
file_name : string
);
port (
clk : in std_logic;
file_output : out std_logic_vector(data_width-1 downto 0) := (others => '0')
);
end entity file_io;
architecture behaviour of file_io is
impure function get_line_count return positive is
file file_pointer : text;
variable line_data : line;
variable lineCount : natural := 0;
begin
file_open(file_pointer, file_name, read_mode);
while not endfile(file_pointer) loop
readline(file_pointer, line_data);
lineCount := lineCount + 1;
end loop;
file_close(file_pointer);
return lineCount;
end function get_line_count;
constant memory_size : positive := get_line_count;
subtype data_type is std_logic_vector(data_width-1 downto 0);
type memory_type is array (0 to memory_size-1) of data_type;
impure function get_data return memory_type is
file file_pointer : text;
variable line_data : line;
variable line_value : bit_vector(data_width-1 downto 0);
variable memory : memory_type;
variable index : natural := 0;
begin
file_open(file_pointer, file_name, read_mode);
while not endfile(file_pointer) loop
readline(file_pointer, line_data);
read(line_data, line_value);
memory(index) := to_stdlogicvector(line_value);
index := index + 1;
end loop;
file_close(file_pointer);
return memory;
end function get_data;
constant memory : memory_type := get_data;
signal index : natural := 0;
begin
process(clk)
begin
if rising_edge(clk) then
file_output <= memory(index);
if (index < memory_size-1) then
index <= index + 1;
else
index <= 0;
end if;
end if;
end process;
end architecture behaviour;
和测试台：
library IEEE;
use IEEE.std_logic_1164.all;
entity file_io_tb is
end entity file_io_tb;
architecture behaviour of file_io_tb is
signal clk : std_logic := '0';
constant data_width : positive := 4;
signal data : std_logic_vector(data_width-1 downto 0);
begin
file_io_inst : entity work.file_io
generic map(
data_width => 4,
file_name => "data_file.txt"
)
port map(
clk => clk,
file_output => data
);
clk_prc : process
begin
loop
clk <= '0', '1' after 1 ns;
wait for 2 ns;
end loop;
end process;
end architecture behaviour;
data_file.txt 刚好包含
0101
1010
1100
0011
...
这对我来说很好...
查看您的其他问题 -
合并该修复并使用方法 J.H。 Bonarius 建议产生 Minimal, Complete and Verifiable example:
library ieee;
use ieee.std_logic_1164.all;
PACKAGE io IS
type memory is array (natural range<>) of std_logic_vector(3 downto 0);
function iswhitespace (inpstr: in string) return boolean;
END;
package body io is
function iswhitespace (inpstr: in string) return boolean is
constant NBSP: character := character'val(128);
begin
for i in inpstr'range loop
if inpstr(i) /= ' ' and inpstr(i) /= NBSP and inpstr(i) /= HT then
exit;
elsif i = inpstr'RIGHT then
return TRUE;
end if;
end loop;
return FALSE;
end function;
end package body;
library ieee;
use ieee.std_logic_1164.all;
use work.io.all;
entity File_io is
generic (
constant MEMORY_SIZE: natural := 42;
constant filename: string := "C:\Users\ChowdaryS\Downloads\topo.bin"
);
port (
clk: in std_logic;
Data_memory: out memory (0 to MEMORY_SIZE - 1)
);
end entity;
architecture foo of File_io is
signal mem: memory (0 to MEMORY_SIZE - 1); -- ADDED subtype indication
use ieee.numeric_std.all; -- MISSING cntext item
use std.textio.all;
signal mem_inited: boolean := FALSE; -- ADDED
begin
process(clk)
file f: text open read_mode is filename;
variable L: line;
variable i: integer:= 0;
variable b: bit_vector(3 downto 0);
begin
if not mem_inited then
i := 0;
while not endfile(f) loop
readline(f, L);
while L.all'length >= b'length and not iswhitespace(L.all) loop
read(L, b);
mem(i) <= to_stdlogicvector(b);
i := i + 1;
end loop;
end loop;
report "mem values loaded = " & integer'image(i);
mem_inited <= TRUE;
end if;
end process;
Data_memory <= mem;
end architecture foo;
有变化。函数 iswhitespace 已添加到包 io 中。您可以看到上面提到的权衡问题以及是否需要。
对输出端口的分配已移出进程。假定您将在该过程中对 mem 进行某种写入。
还有一个测试台实例化 file_io 并确定内存数组的大小，将其作为通用传递。
library ieee;
use ieee.std_logic_1164.all;
use work.io.all;
entity file_io_tb is
end entity;
architecture foo of file_io_tb is
constant MEMSIZ: natural := 16;
constant filename: string := "topo.bin"; -- found locally.
signal clk: std_logic := '0';
signal Data_memory: memory (0 to MEMSIZ - 1);
use std.textio.all;
impure function getarraysize return natural is
variable L: Line;
variable i: natural;
variable b: bit_vector (3 downto 0);
file f: text open read_mode is filename;
begin
i := 0;
while not endfile(f) loop
readline(f, L);
while L.all'length >= b'length and not iswhitespace(L.all) loop
read(L, b);
i := i + 1;
end loop;
end loop;
report " memory size = " & integer'image(i);
return i;
end function;
begin
DUT:
entity work.file_io
generic map (MEMORY_SIZE => getarraysize, filename => filename)
port map (
clk => clk,
Data_memory => Data_memory
);
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if now > 50 ns then
wait;
end if;
end process;
end architecture;
该功能是在细化时执行文件读取以设置通用。
我们看到初始化内存：
使用的 topo.bin 副本在第一行有四个尾随空格：
10101100 11010100 10101100 11010100
11111110 10111001 11111110 10111001
波形中显示的值与来自 topo.bin.
的以上两行匹配（所有这些都是为了在另一个问题中找到空白问题而写的）。