基于LUT4组件的LUT5组件结构说明

Question

请问如何在LUT4组件的基础上正确描述LUT5的结构组件，问题就出在端口的正确映射上。

Entity LUT5 is
Port(
  A,B,C,D,E : in std_logic;
  Z         : out std_logic;
);
End LUT5;

Architecture Behaviour of LUT5 is
Component LUT4
Port(
  A,B,C,D : in std_logic;
  Z       : out std_logic;
);
End Component;
Begin
   ??????
End
End Architecture

Answer 1

您可以使用两个四输入查找 table 表示五输入查找 table，选择器根据第五位在输出之间进行选择：

library ieee;
use ieee.std_logic_1164.all;

entity lut5 is
    generic (
        LUTVAL: std_logic_vector (0 to 31)
    );
    port (
      a, b, c, d, e:    in  std_logic;
      z :               out std_logic
    );
end entity  lut5;

architecture behaviour of lut5 is
    component mux2 is
        port (
            a:  in  std_logic;
            b:  in  std_logic;
            s:  in  std_logic;
            y:  out std_logic
        );
    end component;
    component lut4 is
        generic (
            LUTVAL:  std_logic_vector (0 to 15)
        );
        port (
          a, b, c, d:   in  std_logic;
          z:            out std_logic
         );
    end component;
    signal z0, z1:      std_logic;
begin
LUT4_0:
    lut4
        generic map (
            LUTVAL => LUTVAL(0 to 15)
        )
        port map (
            a => a,
            b => b,
            c => c,
            d => d,
            z => z0
        );
LUT4_1:
    lut4
        generic map (
            LUTVAL => LUTVAL(16 to 31)
        )
        port map (
            a => a,
            b => b,
            c => c,
            d => d,
            z => z1
        );   
MUX_2_1:
    mux2
        port map (
            a => z0,
            b => z1,
            s => e,
            y => z
        );
end architecture;

泛型是一种从设计模型的顶层传递查找 table 内容的方法。

添加一个小测试平台：

library ieee;
use ieee.std_logic_1164.all;

entity lut5_tb is
end entity;

architecture foo of lut5_tb is
    signal a, b, c, d, e:   std_logic := '0';
    signal z:               std_logic;
    constant LUTVAL:        std_logic_vector (0 to 31) := x"A2201000";
    signal index:           natural;
begin
DUT:
    entity work.lut5
    generic map (
        LUTVAL => LUTVAL
    )
    port map (
        a => a,
        b => b,
        c => c,
        d => d,
        e => e,
        z => z
    );
STIMULI:
    process
        use ieee.numeric_std.all;
    begin
        for i in LUTVAL'RANGE loop
            (e, d, c, b, a) <= to_unsigned(i,5);
            index <= i;
            wait for 10 ns;
        end loop;
        wait;
    end process;
end architecture;

而且我们可以看到它执行的是五输入查找 table:

您可以使用添加的索引信号随时间计算 z 输出中的位，并发现输出重构了 32 位 LUTVAL (x"A2201000")。

这里是遗漏的点点滴滴：

library ieee;
use ieee.std_logic_1164.all;

entity mux2 is
    port (
        a:  in  std_logic;
        b:  in  std_logic;
        s:  in  std_logic;
        y:  out std_logic
    );
end entity;

architecture foo of mux2 is
begin
    y <= a when s = '0' else
         b;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity lut4 is
    generic (
        LUTVAL:  std_logic_vector (0 to 15)
    );
    port (
      a, b, c, d:   in  std_logic;
      z:            out std_logic
     );
end entity;

architecture foo of lut4 is
    constant lut:   std_logic_vector := LUTVAL;
    use ieee.numeric_std.all;
begin
LOOKUP:
    z <= lut(to_integer(unsigned'(d,c,b,a)));
end architecture;

基于LUT4组件的LUT5组件结构说明

Structural description of LUT5 component based on LUT4 component

vhdl