如何将 VHDL std_logic_vector 初始化为“0001”

Question

我想从默认的“0001”而不是“0000”初始化我的向量，因为我正在做一个 "automatic" 4 位乘法器并且 (x * 0) 没有用，所以我想跳过“0000”值。这是我的实体：

ENTITY multiplier IS
PORT (
    clk, rst : IN std_logic;
    q, r : INOUT std_logic_vector (3 DOWNTO 0)  := "0001"; -- this not work
    f : OUT std_logic_vector(7 DOWNTO 0)
); 
END multiplier;

Answer 1

使用中间信号

library ieee;
use ieee.std_logic_1164.all;

entity multiplier IS
    port (
        clk : in std_logic;
        rst : in std_logic;
        q : out std_logic_vector(3 downto 0);
        r : out std_logic_vector(3 downto 0);
        f : out std_logic_vector(7 downto 0)
    ); 
end entity;

architecture rtl of multiplier is
    use ieee.numeric_std.all;
    signal q_temp: unsigned(3 downto 0) := "0001"; -- or signed
    signal r_temp: unsigned(3 downto 0) := "0001"; -- or signed
begin
    [...your code...]
    q <= std_logic_vector(q_temp);
    r <= std_logic_vector(r_temp);
end architecture;

如何将 VHDL std_logic_vector 初始化为“0001”

How to initialize a VHDL std_logic_vector to "0001"

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