使用输入生成组件或驱动信号

Question

我正在尝试创建具有以下行为的架构：

entity component1 is
    generic (
        debounce_ticks          : natural range 0 to natural'high
    );
    port (
        rst                     : in    STD_LOGIC;
        clk                     : in    STD_LOGIC;
        sclk                    : in    STD_LOGIC;
        [...]              
    );
end component1;
architecture Behavioral of component1 is
     signal sclk_debounced       : STD_LOGIC;
[...]
begin
debouncer:
    if debounce_ticks > 0 generate
        sclk_debouncer : entity work.static_debouncer
        generic map (
            debounce_ticks => debounce_ticks
        )
        port map (
            clk => clk,
            pulse_in => sclk,
            pulse_out => sclk_debounced
        );
    else --Or something
       sclk_debounced <= sclk
    end generate debouncer;
[..]
end Behavioral;

所以，我有这个信号，我想将它连接到一个输入或基于一个通用的组件循环。

我怎样才能做到这一点？

Answer 1

if generate 语句不支持 else 子句，因此您需要反转检查以模拟 else。您还需要另一个 if generate.

的第二个标签

begin
debouncer:
    if debounce_ticks > 0 generate
        sclk_debouncer : entity work.static_debouncer
        generic map (
            debounce_ticks => debounce_ticks
        )
        port map (
            clk => clk,
            pulse_in => sclk,
            pulse_out => sclk_debounced
        );
    end generate debouncer;
no_debouncer:
    if debounce_ticks <= 0 generate
       sclk_debounced <= sclk
    end generate no_debouncer;
[...]

Answer 2

您需要进行两项更改：

component是保留字，不能作为标识符使用。
else

generate

重命名实体：

entity component1 is
  generic (
    debounce_ticks          : natural range 0 to natural'high
  );
  port (
    rst                     : in    STD_LOGIC;
    clk                     : in    STD_LOGIC;
    sclk                    : in    STD_LOGIC;
    -- [...]              
  );
end entity component1;

固定生成语句：

architecture Behavioral of component1 is
  signal sclk_debounced       : STD_LOGIC;
  -- [...]
begin
  debouncer: if debounce_ticks > 0 generate
    sclk_debouncer : entity work.static_debouncer
      generic map (
        debounce_ticks => debounce_ticks
      )
      port map (
        clk => clk,
        pulse_in => sclk,
        pulse_out => sclk_debounced
      );
  else generate --Or something
    sclk_debounced <= sclk
  end generate debouncer;
  -- [..]
end architecture Behavioral;

使用输入生成组件或驱动信号

Either generate a component or drive signal with input

vhdl