Error (10686): SystemVerilog error at file.sv(8): InstAddress has an aggregate value

Question

我正在尝试编译以下 SystemVerilog，但出现以下错误 "Error (10686): SystemVerilog error at InstRom.sv(8): InstAddress has an aggregate value."

module InstRom#(parameter A = 16, parameter W = 9)
(
input InstAddress[A-1:0],
output logic InstOut[W-1:0]
);
    logic[W-1:0] instr_rom[2**(A)];
    always_comb InstOut = instr_rom[InstAddress];

    initial begin
        $readmemb("cordic.txt", instr_rom);
    end
endmodule

我做错了什么？

Answer 1

InstAddress 是 bit 的解压缩数组，而不是 bit 向量（即打包数组）。这同样适用于 InstOut。将声明更改为

input logic [A-1:0] InstAddress,
output logic [W-1:0] InstOut

你的代码应该可以工作。

Error (10686): SystemVerilog error at file.sv(8): InstAddress has an aggregate value

Error (10686): SystemVerilog error at file.sv(8): InstAddress has an aggregate value

system-verilog